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| author | xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> | 2021-02-20 14:50:43 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-02-23 02:27:35 +0000 |
| commit | cdb5b56303a53bd1866974d9d56c72c25667cedf (patch) | |
| tree | 177ba091f84007361a126205ee60cce5b0e84232 /src/mainboard/google/oak | |
| parent | a09559501c06e3cab420908bd667af4486ec0ba5 (diff) | |
| download | coreboot-cdb5b56303a53bd1866974d9d56c72c25667cedf.tar.xz | |
mb/google/oak: Add new DRAM modules K4E6E304EC-EGCG-4GB
Samsung K4E6E304EC-EGCG-4GB # 1011
BUG=b:179455694
BRANCH=oak
TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge,
update FW to DUTs,these DUTs can pass stress test under run-in.
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Change-Id: I02cc34157fd03edb7d715a23ed404abc40ef8ccc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50978
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/oak')
| -rw-r--r-- | src/mainboard/google/oak/sdram_configs.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EC-EGCG-4GB.inc | 116 |
2 files changed, 117 insertions, 1 deletions
diff --git a/src/mainboard/google/oak/sdram_configs.c b/src/mainboard/google/oak/sdram_configs.c index 34a80146c0..c3da0b0d46 100644 --- a/src/mainboard/google/oak/sdram_configs.c +++ b/src/mainboard/google/oak/sdram_configs.c @@ -16,7 +16,7 @@ static const struct mt8173_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-MT52L256M32D1PF-2GB.inc" /* ram_code = 1000 */ #include "sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc" /* ram_code = 1001 */ #include "sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc" /* ram_code = 1010 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */ +#include "sdram_inf/sdram-lpddr3-K4E6E304EC-EGCG-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */ diff --git a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EC-EGCG-4GB.inc b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EC-EGCG-4GB.inc new file mode 100644 index 0000000000..7e034035ca --- /dev/null +++ b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EC-EGCG-4GB.inc @@ -0,0 +1,116 @@ +{ /* 4GB (16Gb + 16Gb) for dual rank dram setting */ + { + .impedance_drvp = 0x9, + .impedance_drvn = 0xb, + .datlat_ucfirst = 19, + + .ca_train = { + [CHANNEL_A] = { 2, 1, 1, 4, 3, 0, 0, 0, 0, 0}, + [CHANNEL_B] = { 0, 0, 0, 0, 0, 4, 3, 2, 3, 4} + }, + + .ca_train_center = { + [CHANNEL_A] = 0, + [CHANNEL_B] = 0 + }, + + .wr_level = { + [CHANNEL_A] = { 5, 6, 5, 6}, + [CHANNEL_B] = { 6, 4, 5, 3} + }, + + .gating_win = { + [CHANNEL_A] = { + { 29, 64}, + { 29, 64} + }, + [CHANNEL_B] = { + { 29, 72}, + { 29, 72} + } + }, + + .rx_dqs_dly = { + [CHANNEL_A] = 0xd0b0909, + [CHANNEL_B] = 0xa090809 + }, + + .rx_dq_dly = { + [CHANNEL_A] = { + 0x0020202, + 0x4030102, + 0x2040100, + 0x1020102, + 0x1050100, + 0x5040403, + 0x5050706, + 0x0030304 + }, + [CHANNEL_B] = { + 0x2020202, + 0x5020200, + 0x1010200, + 0x2000100, + 0x1030100, + 0x2040202, + 0x2040503, + 0x0010103 + } + }, + }, + { + .actim = 0xaafd478c, + .actim1 = 0x91001f59, + .actim05t = 0x000025e1, + .conf1 = 0x00048403, + .conf2 = 0x030000a9, + .ddr2ctl = 0x000063b1, + .gddr3ctl1 = 0x11000000, + .misctl0 = 0x21000000, + .pd_ctrl = 0xd1976442, + .rkcfg = 0x002156c1, + .test2_3 = 0xbfc70401, + .test2_4 = 0x2801110d + }, + { + .cona = 0xa053a057, + .conb = 0x17283544, + .conc = 0x0a1a0b1a, + .cond = 0x00000000, + .cone = 0xffff0848, + .conf = 0x08420000, + .cong = 0x2b2b2a38, + .conh = 0x00000000, + .conm_1 = 0x40000500, + .conm_2 = 0x400005ff, + .mdct_1 = 0x80030303, + .mdct_2 = 0x34220c3f, + .test0 = 0xcccccccc, + .test1 = 0xcccccccc, + .testb = 0x00060124, + .testc = 0x38470000, + .testd = 0x00000000, + .arba = 0x7f077a49, + .arbc = 0xa0a070dd, + .arbd = 0x07007046, + .arbe = 0x40407046, + .arbf = 0xa0a070c6, + .arbg = 0xffff7047, + .arbi = 0x20406188, + .arbj = 0x9719595e, + .arbk = 0x64f3fc79, + .slct_1 = 0x00010800, + .slct_2 = 0xff03ff00, + .bmen = 0x00ff0001 + }, + { + .mrs_1 = 0x00830001, + .mrs_2 = 0x001c0002, + .mrs_3 = 0x00010003, + .mrs_10 = 0x00ff000a, + .mrs_11 = 0x0000000b, + .mrs_63 = 0x0000003f + }, + .type = TYPE_LPDDR3, + .dram_freq = 896 * MHz, +}, |