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authorTristan Shieh <tristan.shieh@mediatek.com>2018-07-09 18:59:32 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-07-20 13:50:54 +0000
commit71d227b1085b5f54b11a6fcfa9419597ee5c9f56 (patch)
tree49ba7259011ef038a6b8f9aa1808523b650115fe /src/mainboard/google/oak
parentccb62960db3eff2d4c2905710ba99ba90f24bcdc (diff)
downloadcoreboot-71d227b1085b5f54b11a6fcfa9419597ee5c9f56.tar.xz
mediatek: Share GPIO code among similar SOCs
Refactor GPIO code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google/oak')
-rw-r--r--src/mainboard/google/oak/bootblock.c43
-rw-r--r--src/mainboard/google/oak/chromeos.c12
-rw-r--r--src/mainboard/google/oak/gpio.h61
-rw-r--r--src/mainboard/google/oak/mainboard.c81
4 files changed, 97 insertions, 100 deletions
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c
index fe9c9ba8c4..9cba3b4d23 100644
--- a/src/mainboard/google/oak/bootblock.c
+++ b/src/mainboard/google/oak/bootblock.c
@@ -22,17 +22,16 @@
#include <soc/i2c.h>
#include <soc/mt6391.h>
#include <soc/pericfg.h>
-#include <soc/pinmux.h>
#include <soc/spi.h>
#include "gpio.h"
static void i2c_set_gpio_pinmux(void)
{
- gpio_set_mode(PAD_SDA1, PAD_SDA1_FUNC_SDA1);
- gpio_set_mode(PAD_SCL1, PAD_SCL1_FUNC_SCL1);
- gpio_set_mode(PAD_SDA4, PAD_SDA4_FUNC_SDA4);
- gpio_set_mode(PAD_SCL4, PAD_SCL4_FUNC_SCL4);
+ gpio_set_mode(GPIO(SDA1), PAD_SDA1_FUNC_SDA1);
+ gpio_set_mode(GPIO(SCL1), PAD_SCL1_FUNC_SCL1);
+ gpio_set_mode(GPIO(SDA4), PAD_SDA4_FUNC_SDA4);
+ gpio_set_mode(GPIO(SCL4), PAD_SCL4_FUNC_SCL4);
}
static void nor_set_gpio_pinmux(void)
@@ -44,23 +43,23 @@ static void nor_set_gpio_pinmux(void)
* 3: 16mA
*/
/* EINT4: 0x10005B20[14:13] */
- clrsetbits_le16(&mt8173_gpio->drv_mode[2].val, 0xf << 12, 2 << 13);
+ clrsetbits_le16(&mtk_gpio->drv_mode[2].val, 0xf << 12, 2 << 13);
/* EINT5~EINT9: 0x10005B30[2:1] */
- clrsetbits_le16(&mt8173_gpio->drv_mode[3].val, 0xf << 0, 2 << 1),
-
- gpio_set_pull(PAD_EINT4, GPIO_PULL_ENABLE, GPIO_PULL_UP);
- gpio_set_pull(PAD_EINT5, GPIO_PULL_ENABLE, GPIO_PULL_UP);
- gpio_set_pull(PAD_EINT6, GPIO_PULL_ENABLE, GPIO_PULL_UP);
- gpio_set_pull(PAD_EINT7, GPIO_PULL_ENABLE, GPIO_PULL_UP);
- gpio_set_pull(PAD_EINT8, GPIO_PULL_ENABLE, GPIO_PULL_UP);
- gpio_set_pull(PAD_EINT9, GPIO_PULL_ENABLE, GPIO_PULL_UP);
-
- gpio_set_mode(PAD_EINT4, PAD_EINT4_FUNC_SFWP_B);
- gpio_set_mode(PAD_EINT5, PAD_EINT5_FUNC_SFOUT);
- gpio_set_mode(PAD_EINT6, PAD_EINT6_FUNC_SFCS0);
- gpio_set_mode(PAD_EINT7, PAD_EINT7_FUNC_SFHOLD);
- gpio_set_mode(PAD_EINT8, PAD_EINT8_FUNC_SFIN);
- gpio_set_mode(PAD_EINT9, PAD_EINT9_FUNC_SFCK);
+ clrsetbits_le16(&mtk_gpio->drv_mode[3].val, 0xf << 0, 2 << 1),
+
+ gpio_set_pull(GPIO(EINT4), GPIO_PULL_ENABLE, GPIO_PULL_UP);
+ gpio_set_pull(GPIO(EINT5), GPIO_PULL_ENABLE, GPIO_PULL_UP);
+ gpio_set_pull(GPIO(EINT6), GPIO_PULL_ENABLE, GPIO_PULL_UP);
+ gpio_set_pull(GPIO(EINT7), GPIO_PULL_ENABLE, GPIO_PULL_UP);
+ gpio_set_pull(GPIO(EINT8), GPIO_PULL_ENABLE, GPIO_PULL_UP);
+ gpio_set_pull(GPIO(EINT9), GPIO_PULL_ENABLE, GPIO_PULL_UP);
+
+ gpio_set_mode(GPIO(EINT4), PAD_EINT4_FUNC_SFWP_B);
+ gpio_set_mode(GPIO(EINT5), PAD_EINT5_FUNC_SFOUT);
+ gpio_set_mode(GPIO(EINT6), PAD_EINT6_FUNC_SFCS0);
+ gpio_set_mode(GPIO(EINT7), PAD_EINT7_FUNC_SFHOLD);
+ gpio_set_mode(GPIO(EINT8), PAD_EINT8_FUNC_SFIN);
+ gpio_set_mode(GPIO(EINT9), PAD_EINT9_FUNC_SFCK);
}
void bootblock_mainboard_early_init(void)
@@ -83,7 +82,7 @@ void bootblock_mainboard_init(void)
/* SPI_LEVEL_ENABLE: Enable 1.8V to 3.3V level shifter for EC SPI bus */
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4 &&
board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 8)
- gpio_output(PAD_SRCLKENAI2, 1);
+ gpio_output(GPIO(SRCLKENAI2), 1);
/* Init i2c bus 2 Timing register for TPM */
mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);
diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c
index 42145f7f1d..93791fb37f 100644
--- a/src/mainboard/google/oak/chromeos.c
+++ b/src/mainboard/google/oak/chromeos.c
@@ -35,14 +35,14 @@ void setup_chromeos_gpios(void)
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
- {WRITE_PROTECT, ACTIVE_LOW,
+ {WRITE_PROTECT.id, ACTIVE_LOW,
gpio_get(WRITE_PROTECT), "write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- {LID, ACTIVE_HIGH, -1, "lid"},
- {POWER_BUTTON, ACTIVE_HIGH, -1, "power"},
- {EC_IN_RW, ACTIVE_HIGH, -1, "EC in RW"},
- {EC_IRQ, ACTIVE_LOW, -1, "EC interrupt"},
- {CR50_IRQ, ACTIVE_HIGH, -1, "TPM interrupt"},
+ {LID.id, ACTIVE_HIGH, -1, "lid"},
+ {POWER_BUTTON.id, ACTIVE_HIGH, -1, "power"},
+ {EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"},
+ {EC_IRQ.id, ACTIVE_LOW, -1, "EC interrupt"},
+ {CR50_IRQ.id, ACTIVE_HIGH, -1, "TPM interrupt"},
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
diff --git a/src/mainboard/google/oak/gpio.h b/src/mainboard/google/oak/gpio.h
index 4bed95d546..666267170a 100644
--- a/src/mainboard/google/oak/gpio.h
+++ b/src/mainboard/google/oak/gpio.h
@@ -15,39 +15,38 @@
#ifndef __MAINBOARD_GOOGLE_OAK_GPIO_H__
#define __MAINBOARD_GOOGLE_OAK_GPIO_H__
-#include <soc/pinmux.h>
+#include <soc/gpio.h>
-#define LID ((IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) ? PAD_KPROW1 \
- : ((board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7) ? PAD_EINT12 \
- : PAD_SPI_CK))
+#if IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)
+#define LID GPIO(KPROW1)
+#define RAM_ID_1 GPIO(DSI_TE)
+#define RAM_ID_2 GPIO(RDP1_A)
+#else
+#define LID ((board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7) ? \
+ GPIO(EINT12) : GPIO(SPI_CK))
+#define RAM_ID_1 GPIO(RCN_A)
+#define RAM_ID_2 GPIO(RCP_A)
+#endif
-#define RAM_ID_1 ((IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) ? PAD_DSI_TE \
- : PAD_RCN_A)
-
-#define RAM_ID_2 ((IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) ? PAD_RDP1_A \
- : PAD_RCP_A)
-
-enum {
- /* Board ID related GPIOS. */
- BOARD_ID_0 = PAD_RDN3_A,
- BOARD_ID_1 = PAD_RDP3_A,
- BOARD_ID_2 = PAD_RDN2_A,
- /* RAM ID related GPIOS. */
- RAM_ID_0 = PAD_RDP2_A,
- RAM_ID_3 = PAD_RDN1_A,
- /* Write Protect */
- WRITE_PROTECT = PAD_EINT4,
- /* Power button */
- POWER_BUTTON = PAD_EINT14,
- /* EC Interrupt */
- EC_IRQ = PAD_EINT0,
- /* EC in RW signal */
- EC_IN_RW = PAD_DAIPCMIN,
- /* EC AP suspend */
- EC_SUSPEND_L = PAD_KPROW1,
- /* Cr50 interrupt */
- CR50_IRQ = PAD_EINT16,
-};
+/* Board ID related GPIOS. */
+#define BOARD_ID_0 GPIO(RDN3_A)
+#define BOARD_ID_1 GPIO(RDP3_A)
+#define BOARD_ID_2 GPIO(RDN2_A)
+/* RAM ID related GPIOS. */
+#define RAM_ID_0 GPIO(RDP2_A)
+#define RAM_ID_3 GPIO(RDN1_A)
+/* Write Protect */
+#define WRITE_PROTECT GPIO(EINT4)
+/* Power button */
+#define POWER_BUTTON GPIO(EINT14)
+/* EC Interrupt */
+#define EC_IRQ GPIO(EINT0)
+/* EC in RW signal */
+#define EC_IN_RW GPIO(DAIPCMIN)
+/* EC AP suspend */
+#define EC_SUSPEND_L GPIO(KPROW1)
+/* Cr50 interrupt */
+#define CR50_IRQ GPIO(EINT16)
void setup_chromeos_gpios(void);
diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c
index 82e6fc06f6..2510a6533e 100644
--- a/src/mainboard/google/oak/mainboard.c
+++ b/src/mainboard/google/oak/mainboard.c
@@ -33,7 +33,6 @@
#include <soc/mt6311.h>
#include <soc/mt6391.h>
#include <soc/mtcmos.h>
-#include <soc/pinmux.h>
#include <soc/pll.h>
#include <soc/usb.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -51,7 +50,7 @@ static void configure_ext_buck(void)
case 3:
case 4:
/* rev-3 and rev-4 use mt6311 as external buck */
- gpio_output(PAD_EINT15, 1);
+ gpio_output(GPIO(EINT15), 1);
udelay(500);
mt6311_probe(EXT_BUCK_I2C_BUS);
break;
@@ -70,9 +69,9 @@ static void configure_touchscreen(void)
{
/* Pull low reset gpio for 500us and then pull high */
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT >= 7) {
- gpio_output(PAD_PCM_SYNC, 0);
+ gpio_output(GPIO(PCM_SYNC), 0);
udelay(500);
- gpio_output(PAD_PCM_SYNC, 1);
+ gpio_output(GPIO(PCM_SYNC), 1);
}
}
@@ -89,14 +88,14 @@ static void configure_audio(void)
/* reset ALC5676 */
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5)
- gpio_output(PAD_LCM_RST, 1);
+ gpio_output(GPIO(LCM_RST), 1);
/* SoC I2S */
- gpio_set_mode(PAD_I2S0_LRCK, PAD_I2S0_LRCK_FUNC_I2S1_WS);
- gpio_set_mode(PAD_I2S0_BCK, PAD_I2S0_BCK_FUNC_I2S1_BCK);
- gpio_set_mode(PAD_I2S0_MCK, PAD_I2S0_MCK_FUNC_I2S1_MCK);
- gpio_set_mode(PAD_I2S0_DATA0, PAD_I2S0_DATA0_FUNC_I2S1_DO_1);
- gpio_set_mode(PAD_I2S0_DATA1, PAD_I2S0_DATA1_FUNC_I2S2_DI_2);
+ gpio_set_mode(GPIO(I2S0_LRCK), PAD_I2S0_LRCK_FUNC_I2S1_WS);
+ gpio_set_mode(GPIO(I2S0_BCK), PAD_I2S0_BCK_FUNC_I2S1_BCK);
+ gpio_set_mode(GPIO(I2S0_MCK), PAD_I2S0_MCK_FUNC_I2S1_MCK);
+ gpio_set_mode(GPIO(I2S0_DATA0), PAD_I2S0_DATA0_FUNC_I2S1_DO_1);
+ gpio_set_mode(GPIO(I2S0_DATA1), PAD_I2S0_DATA1_FUNC_I2S2_DI_2);
/* codec ext MCLK ON */
mt6391_gpio_output(MT6391_KP_COL4, 1);
@@ -108,7 +107,7 @@ static void configure_audio(void)
break;
case 5:
case 6:
- gpio_set_mode(PAD_UCTS0, PAD_UCTS0_FUNC_I2S2_DI_1);
+ gpio_set_mode(GPIO(UCTS0), PAD_UCTS0_FUNC_I2S2_DI_1);
mt6391_gpio_output(MT6391_KP_COL5, 1);
break;
default:
@@ -128,25 +127,25 @@ static void configure_usb(void)
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 3) {
/* Type C port 0 Over current alert pin */
- gpio_input_pullup(PAD_MSDC3_DSL);
+ gpio_input_pullup(GPIO(MSDC3_DSL));
if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) {
/* Enable USB3 type A port 0 5V load switch */
- gpio_output(PAD_CM2MCLK, 1);
+ gpio_output(GPIO(CM2MCLK), 1);
/* USB3 Type A port 0 power over current alert pin */
- gpio_input_pullup(PAD_CMPCLK);
+ gpio_input_pullup(GPIO(CMPCLK));
}
/* Type C port 1 over current alert pin */
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7)
- gpio_input_pullup(PAD_PCM_SYNC);
+ gpio_input_pullup(GPIO(PCM_SYNC));
}
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4 &&
board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7)
{
/* USB 2.0 type A port over current interrupt pin(low active) */
- gpio_input_pullup(PAD_UCTS2);
+ gpio_input_pullup(GPIO(UCTS2));
/* USB 2.0 type A port BC1.2 STATUS(low active) */
- gpio_input_pullup(PAD_AUD_DAT_MISO);
+ gpio_input_pullup(GPIO(AUD_DAT_MISO));
}
}
@@ -157,7 +156,7 @@ static void configure_usb_hub(void)
/* set usb hub reset pin (low active) to high */
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4)
- gpio_output(PAD_UTXD3, 1);
+ gpio_output(GPIO(UTXD3), 1);
}
/* Setup backlight control pins as output pin and power-off by default */
@@ -166,70 +165,70 @@ static void configure_backlight(void)
/* Configure PANEL_LCD_POWER_EN */
switch (board_id() + CONFIG_BOARD_ID_ADJUSTMENT) {
case 3:
- gpio_output(PAD_UCTS2, 0);
+ gpio_output(GPIO(UCTS2), 0);
break;
case 4:
- gpio_output(PAD_SRCLKENAI, 0);
+ gpio_output(GPIO(SRCLKENAI), 0);
break;
default:
- gpio_output(PAD_UTXD2, 0);
+ gpio_output(GPIO(UTXD2), 0);
break;
}
- gpio_output(PAD_DISP_PWM0, 0); /* DISP_PWM0 */
- gpio_output(PAD_PCM_TX, 0); /* PANEL_POWER_EN */
+ gpio_output(GPIO(DISP_PWM0), 0); /* DISP_PWM0 */
+ gpio_output(GPIO(PCM_TX), 0); /* PANEL_POWER_EN */
}
static void configure_display(void)
{
/* board from Rev2 */
- gpio_output(PAD_CMMCLK, 1); /* PANEL_3V3_ENABLE */
+ gpio_output(GPIO(CMMCLK), 1); /* PANEL_3V3_ENABLE */
/* vgp2 set to 3.3V for ps8640 */
mt6391_configure_ldo(LDO_VGP2, LDO_3P3);
- gpio_output(PAD_URTS0, 0); /* PS8640_SYSRSTN */
+ gpio_output(GPIO(URTS0), 0); /* PS8640_SYSRSTN */
/* PS8640_1V2_ENABLE */
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT == 4)
- gpio_output(PAD_SRCLKENAI2, 1);
+ gpio_output(GPIO(SRCLKENAI2), 1);
else
- gpio_output(PAD_URTS2, 1);
+ gpio_output(GPIO(URTS2), 1);
/* delay 2ms for vgp2 and PS8640_1V2_ENABLE stable */
mdelay(2);
/* PS8640_PDN */
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4)
- gpio_output(PAD_LCM_RST, 1);
+ gpio_output(GPIO(LCM_RST), 1);
else
- gpio_output(PAD_UCTS0, 1);
- gpio_output(PAD_PCM_CLK, 1); /* PS8640_MODE_CONF */
- gpio_output(PAD_URTS0, 1); /* PS8640_SYSRSTN */
+ gpio_output(GPIO(UCTS0), 1);
+ gpio_output(GPIO(PCM_CLK), 1); /* PS8640_MODE_CONF */
+ gpio_output(GPIO(URTS0), 1); /* PS8640_SYSRSTN */
/* for level shift(1.8V to 3.3V) on */
udelay(100);
}
static void configure_backlight_rowan(void)
{
- gpio_output(PAD_DAIPCMOUT, 0); /* PANEL_LCD_POWER_EN */
- gpio_output(PAD_DISP_PWM0, 0); /* DISP_PWM0 */
- gpio_output(PAD_PCM_TX, 0); /* PANEL_POWER_EN */
+ gpio_output(GPIO(DAIPCMOUT), 0); /* PANEL_LCD_POWER_EN */
+ gpio_output(GPIO(DISP_PWM0), 0); /* DISP_PWM0 */
+ gpio_output(GPIO(PCM_TX), 0); /* PANEL_POWER_EN */
}
static void configure_display_rowan(void)
{
- gpio_output(PAD_UCTS2, 1); /* VDDIO_EN */
+ gpio_output(GPIO(UCTS2), 1); /* VDDIO_EN */
/* delay 15 ms for panel vddio to stabilize */
mdelay(15);
- gpio_output(PAD_SRCLKENAI2, 1); /* LCD_RESET */
+ gpio_output(GPIO(SRCLKENAI2), 1); /* LCD_RESET */
udelay(20);
- gpio_output(PAD_SRCLKENAI2, 0); /* LCD_RESET */
+ gpio_output(GPIO(SRCLKENAI2), 0); /* LCD_RESET */
udelay(20);
- gpio_output(PAD_SRCLKENAI2, 1); /* LCD_RESET */
+ gpio_output(GPIO(SRCLKENAI2), 1); /* LCD_RESET */
mdelay(20);
/* Rowan panel avdd */
- gpio_output(PAD_URTS2, 1);
+ gpio_output(GPIO(URTS2), 1);
/* Rowan panel avee */
- gpio_output(PAD_URTS0, 1);
+ gpio_output(GPIO(URTS0), 1);
/* panel.delay.prepare */
mdelay(20);
@@ -320,7 +319,7 @@ static void mainboard_init(struct device *dev)
mt6391_gpio_output(MT6391_KP_ROW2, 1);
/* Config SD card detection pin */
- gpio_input_pullup(PAD_EINT1); /* SD_DET */
+ gpio_input_pullup(GPIO(EINT1)); /* SD_DET */
configure_audio();