diff options
author | jun.gao <jun.gao@mediatek.com> | 2015-12-17 16:59:55 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2016-03-12 09:05:35 +0100 |
commit | f059e97cc8887cc28987d92fc00604f62c456824 (patch) | |
tree | cc51c99950fb4564315534f710e14de9b57d6bf9 /src/mainboard/google/oak | |
parent | 72980b15de5507f06e39818f8a9a9dd0c87f4aa5 (diff) | |
download | coreboot-f059e97cc8887cc28987d92fc00604f62c456824.tar.xz |
google/oak: Initialize i2c bus timing register for TPM and external buck
BRANCH=none
BUG=none
TEST=build pass and boot to oak kernel
Change-Id: Id2c3bbb70a1de54a56ee04ecda76178b1bdf1a4d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8641689e008c58e909606c225dddb81dc6457ae9
Original-Change-Id: I96ef8a36bc70594097e9df964934b7e3eca5d5f9
Original-Signed-off-by: jun.gao <jun.gao@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319031
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13108
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/oak')
-rw-r--r-- | src/mainboard/google/oak/bootblock.c | 4 | ||||
-rw-r--r-- | src/mainboard/google/oak/mainboard.c | 10 |
2 files changed, 14 insertions, 0 deletions
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index efb489fb15..49cf5ddf65 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -18,6 +18,7 @@ #include <bootblock_common.h> #include <delay.h> #include <soc/gpio.h> +#include <soc/i2c.h> #include <soc/mt6391.h> #include <soc/pericfg.h> #include <soc/pinmux.h> @@ -78,6 +79,9 @@ void bootblock_mainboard_init(void) /* set nor related GPIO */ nor_set_gpio_pinmux(); + /* Init i2c bus 2 Timing register for TPM */ + mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz); setup_chromeos_gpios(); diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 544041f6a9..1713c9bdf7 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -23,6 +23,7 @@ #include <elog.h> #include <gpio.h> #include <soc/bl31_plat_params.h> +#include <soc/i2c.h> #include <soc/mt6391.h> #include <soc/mtcmos.h> #include <soc/pinmux.h> @@ -53,6 +54,9 @@ static void register_da9212_to_bl31(void) }, }; register_bl31_param(¶m_da9212.h); + + /* Init i2c bus Timing register for da9212 */ + mtk_i2c_bus_init(param_da9212.i2c_bus); #endif } @@ -66,6 +70,9 @@ static void register_mt6311_to_bl31(void) .i2c_bus = 1, }; register_bl31_param(¶m_mt6311.h); + + /* Init i2c bus Timing register for mt6311 */ + mtk_i2c_bus_init(param_mt6311.i2c_bus); #endif } @@ -119,6 +126,9 @@ static void configure_audio(void) mt6391_gpio_output(MT6391_KP_COL4, 1); mt6391_gpio_output(MT6391_KP_COL5, 1); + /* Init i2c bus Timing register for audio codecs */ + mtk_i2c_bus_init(0); + /* set I2S clock to 48KHz */ mt_pll_set_aud_div(48 * KHz); } |