diff options
| author | Jitao Shi <jitao.shi@mediatek.com> | 2017-02-07 08:51:01 +0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2017-04-25 02:36:55 +0200 |
| commit | b927fe19549eaf045e9372f21d1ba19f65fc669f (patch) | |
| tree | cd8883c534918e037499666eea8eb4d6bcdc3a4c /src/mainboard/google/oak | |
| parent | 2332adacaf9776f0eb8335c05bc0e65f9c1b2e3e (diff) | |
| download | coreboot-b927fe19549eaf045e9372f21d1ba19f65fc669f.tar.xz | |
mediatek/mt8173: Add support for Dual DSI output
The MT817x display output pipeline can be configured to drive an 8-lane
MIPI/DSI panel using "dual DSI" mode. For the "dual DSI" video data path,
the UFO block is configured to reorder the data stream into left and right
halves which are then sent by the SPLIT1 block to the DSI0 and DSI1
respectively. The DSI0 and DSI1 outputs are then synchronously clocked at
half the nominal data rate by their respective MIPI_TX0/MIPI_TX1 phys.
Also, update the call sites in oak mainboard to avoid build breakage.
BRANCH=none
BUG=b:35774871
TEST=Boot Rowan in developer mode and see output on the panel
Change-Id: Id47dfd7d9e98689b54398fc8d9142336b41dc29f
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19361
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google/oak')
| -rw-r--r-- | src/mainboard/google/oak/mainboard.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 2e17678cb1..4320f6ec1c 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -212,6 +212,7 @@ static void display_startup(void) struct edid edid; u8 i2c_bus, i2c_addr; int ret; + bool dual_dsi_mode = false; if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 6) { i2c_bus = 0; @@ -231,15 +232,15 @@ static void display_startup(void) edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - mtk_ddp_init(); + mtk_ddp_init(dual_dsi_mode); ret = mtk_dsi_init(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE, - MIPI_DSI_FMT_RGB888, 4, &edid); + MIPI_DSI_FMT_RGB888, 4, dual_dsi_mode, &edid); if (ret < 0) { printk(BIOS_ERR, "dsi init fail\n"); return; } - mtk_ddp_mode_set(&edid); + mtk_ddp_mode_set(&edid, dual_dsi_mode); set_vbe_mode_info_valid(&edid, (uintptr_t)0); } |