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authorMatt DeVillier <matt.devillier@gmail.com>2014-07-13 18:51:28 -0500
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-07-18 08:17:56 +0200
commitae141dd91b7960dd6ed87d57ad4dad0e06eb709e (patch)
tree31d36b4f776cbb0fedc2162813f7c03e772ea249 /src/mainboard/google/panther/chromeos.c
parent1f9653a1bc737587deed507cd173595b180aad8f (diff)
downloadcoreboot-ae141dd91b7960dd6ed87d57ad4dad0e06eb709e.tar.xz
google/panther: general cleanup, file organization (non-functional)
acpi_tables.c: consolidate/organize headers chromeos.c: consolidate/organize headers; move header, #defines outside of #ifdef fadt.c: organize headers gpio.h: rename include guard; add comment to trailing #endif had_verb.h: add include guard; replace manual array size calculation with std header macro lan.c: remove conditional header inclusion; organize headers; remove pre-processor directive indentations mainboard.c: remove conditional header inclusion; organize headers; replace spaced indentations with tab(s); add comment to trailing #endif onboard.h: move fn prototype after #defines; add comment to trailing #endif romstage.c: consolidate/organize headers smihandler.c: organize headers; remove commented-out/dead code; add comment to trailing #endif thermal.h: add comment to trailing #endif Change-Id: Iadafdd1092108c3f52435831fa0103f2457066f1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/6270 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/google/panther/chromeos.c')
-rw-r--r--src/mainboard/google/panther/chromeos.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/src/mainboard/google/panther/chromeos.c b/src/mainboard/google/panther/chromeos.c
index 074f648a68..62165daed2 100644
--- a/src/mainboard/google/panther/chromeos.c
+++ b/src/mainboard/google/panther/chromeos.c
@@ -18,11 +18,12 @@
*/
#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
#include <arch/io.h>
+#include <boot/coreboot_tables.h>
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#define GPIO_SPI_WP 58
#define GPIO_REC_MODE 12
@@ -31,13 +32,11 @@
#define FLAG_REC_MODE 1
#define FLAG_DEV_MODE 2
-#ifndef __PRE_RAM__
-#include <boot/coreboot_tables.h>
-
#define GPIO_COUNT 6
#define ACTIVE_LOW 0
#define ACTIVE_HIGH 1
+#ifndef __PRE_RAM__
static void fill_lb_gpio(struct lb_gpio *gpio, int num,
int polarity, const char *name, int force)
{