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author | Matt DeVillier <matt.devillier@gmail.com> | 2014-07-13 18:51:28 -0500 |
---|---|---|
committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-07-18 08:17:56 +0200 |
commit | ae141dd91b7960dd6ed87d57ad4dad0e06eb709e (patch) | |
tree | 31d36b4f776cbb0fedc2162813f7c03e772ea249 /src/mainboard/google/panther/smihandler.c | |
parent | 1f9653a1bc737587deed507cd173595b180aad8f (diff) | |
download | coreboot-ae141dd91b7960dd6ed87d57ad4dad0e06eb709e.tar.xz |
google/panther: general cleanup, file organization (non-functional)
acpi_tables.c: consolidate/organize headers
chromeos.c: consolidate/organize headers; move header, #defines outside
of #ifdef
fadt.c: organize headers
gpio.h: rename include guard; add comment to trailing #endif
had_verb.h: add include guard; replace manual array size calculation with std
header macro
lan.c: remove conditional header inclusion; organize headers; remove
pre-processor directive indentations
mainboard.c: remove conditional header inclusion; organize headers; replace
spaced indentations with tab(s); add comment to trailing #endif
onboard.h: move fn prototype after #defines; add comment to trailing #endif
romstage.c: consolidate/organize headers
smihandler.c: organize headers; remove commented-out/dead code; add comment
to trailing #endif
thermal.h: add comment to trailing #endif
Change-Id: Iadafdd1092108c3f52435831fa0103f2457066f1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/6270
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/google/panther/smihandler.c')
-rw-r--r-- | src/mainboard/google/panther/smihandler.c | 91 |
1 files changed, 4 insertions, 87 deletions
diff --git a/src/mainboard/google/panther/smihandler.c b/src/mainboard/google/panther/smihandler.c index 2ad249848a..3448648849 100644 --- a/src/mainboard/google/panther/smihandler.c +++ b/src/mainboard/google/panther/smihandler.c @@ -20,12 +20,12 @@ #include <arch/io.h> #include <console/console.h> +#include <cpu/intel/haswell/haswell.h> #include <cpu/x86/smm.h> +#include <northbridge/intel/haswell/haswell.h> +#include <southbridge/intel/lynxpoint/me.h> #include <southbridge/intel/lynxpoint/nvs.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/lynxpoint/me.h> -#include <northbridge/intel/haswell/haswell.h> -#include <cpu/intel/haswell/haswell.h> #include <elog.h> /* GPIO46 controls the WLAN_DISABLE_L signal. */ @@ -49,82 +49,9 @@ int mainboard_io_trap_handler(int smif) * For now, we force the return value to 0 and log all traps to * see what's going on. */ - //gnvs->smif = 0; return 1; } -#if 0 -static u8 mainboard_smi_ec(void) -{ - u8 cmd = 0;// google_chromeec_get_event(); - -#if CONFIG_ELOG_GSMI - /* Log this event */ - if (cmd) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); -#endif - - return cmd; -} -#endif - -/* gpi_sts is GPIO 47:32 */ -void mainboard_smi_gpi(u32 gpi_sts) -{ -#if 0 - if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } -#endif -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - /* Disable USB charging if required */ - switch (slp_typ) { - case 3: - //if (smm_get_gnvs()->s3u0 == 0) - // google_chromeec_set_usb_charge_mode( - // 0, USB_CHARGE_MODE_DISABLED); - //if (smm_get_gnvs()->s3u1 == 0) - // google_chromeec_set_usb_charge_mode( - // 1, USB_CHARGE_MODE_DISABLED); - - /* Prevent leak from standby rail to WLAN rail in S3. */ - //set_gpio(GPIO_WLAN_DISABLE_L, 0); - /* Disable LTE */ - //set_gpio(GPIO_LTE_DISABLE_L, 0); - - /* Enable wake events */ - //google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); - break; - case 5: - //if (smm_get_gnvs()->s5u0 == 0) - // google_chromeec_set_usb_charge_mode( - // 0, USB_CHARGE_MODE_DISABLED); - //if (smm_get_gnvs()->s5u1 == 0) - // google_chromeec_set_usb_charge_mode( - // 1, USB_CHARGE_MODE_DISABLED); - - /* Prevent leak from standby rail to WLAN rail in S5. */ - //set_gpio(GPIO_WLAN_DISABLE_L, 0); - /* Disable LTE */ - //set_gpio(GPIO_LTE_DISABLE_L, 0); - - /* Enable wake events */ - //google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); - break; - } - - /* Disable SCI and SMI events */ - //google_chromeec_set_smi_mask(0); - //google_chromeec_set_sci_mask(0); - - /* Clear pending events that may trigger immediate wake */ - //while (google_chromeec_get_event() != 0); -} - #define APMC_FINALIZE 0xcb static int mainboard_finalized = 0; @@ -144,17 +71,7 @@ int mainboard_smi_apmc(u8 apmc) mainboard_finalized = 1; break; - case APM_CNT_ACPI_ENABLE: - //google_chromeec_set_smi_mask(0); - /* Clear all pending events */ - //while (google_chromeec_get_event() != 0); - //google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - break; - case APM_CNT_ACPI_DISABLE: - //google_chromeec_set_sci_mask(0); - /* Clear all pending events */ - //while (google_chromeec_get_event() != 0); - //google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + default: break; } return 0; |