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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2015-05-18 10:29:06 +0200 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2015-05-27 22:23:05 +0200 |
| commit | 0e90dae584c506b06e7bf3d89064a64db04132bb (patch) | |
| tree | 83876d4f6e39e432789c0bcdb6384068bdcd566b /src/mainboard/google/parrot | |
| parent | 40772a0b5afc7d82a213b005905e2d9e71a6328e (diff) | |
| download | coreboot-0e90dae584c506b06e7bf3d89064a64db04132bb.tar.xz | |
Move TPM code out of chromeos
This code is not specific to ChromeOS and is useful outside of it.
Like with small modifications it can be used to disable TPM altogether.
Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10269
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/parrot')
| -rw-r--r-- | src/mainboard/google/parrot/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/parrot/romstage.c | 10 |
2 files changed, 5 insertions, 6 deletions
diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 07405c6098..9cf390ac79 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index d0fab67edb..a947c48666 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -39,10 +39,8 @@ #include <cpu/x86/msr.h> #include <halt.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif #include <cbfs.h> +#include <tpm.h> #include "ec/compal/ene932/ec.h" static void pch_enable_lpc(void) @@ -197,8 +195,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + if (CONFIG_LPC_TPM) { + init_tpm(boot_mode == 2); + } timestamp_add_now(TS_END_ROMSTAGE); } |