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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2016-02-10 02:36:04 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-12 17:09:05 +0100 |
| commit | 144eea069726903d157f67a2f886dff4575d9b19 (patch) | |
| tree | 995376822269c860e71fbae390a970fab3d587a7 /src/mainboard/google/parrot | |
| parent | c37c7c8b1f3977e362e05945a48ddecf803e20a7 (diff) | |
| download | coreboot-144eea069726903d157f67a2f886dff4575d9b19.tar.xz | |
Make MRC vs native a config rather than making a separate chipset for it.
Tested by making lenovo x230 configurable despite pretty MRC bugs.
Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13658
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/parrot')
| -rw-r--r-- | src/mainboard/google/parrot/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/google/parrot/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/parrot/romstage.c | 25 |
3 files changed, 28 insertions, 1 deletions
diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index e9b55a4ae8..56ebf86fb9 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC + select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_COMPAL_ENE932 select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 0a54566cf6..eacfe57521 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -18,6 +18,8 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x000001d4" register "gpu_pch_backlight" = "0x03aa0000" + register "max_mem_clock_mhz" = "666" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 030f7c467e..5897d13bcf 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -28,6 +28,7 @@ #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> @@ -158,6 +159,30 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) *pei_data = pei_data_template; } +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled power usb oc pin */ + { 0, 0, -1 }, /* P0: Empty */ + { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ + { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ + { 1, 0, 1 }, /* P3: Left USB 3 (OC1) */ + { 0, 0, -1 }, /* P4: Empty */ + { 0, 0, -1 }, /* P5: Empty */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ + { 1, 0, -1 }, /* P8: MiniPCIe (WLAN) (no OC) */ + { 0, 0, -1 }, /* P9: Empty */ + { 1, 0, -1 }, /* P10: Camera (no OC) */ + { 0, 0, -1 }, /* P11: Empty */ + { 0, 0, -1 }, /* P12: Empty */ + { 0, 0, -1 }, /* P13: Empty */ +}; + +void mainboard_get_spd(spd_raw_data *spd) { + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); +} + void mainboard_config_superio(void) { } |