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authorPatrick Rudolph <siro@das-labor.org>2016-02-06 17:42:42 +0100
committerStefan Reinauer <stefan.reinauer@coreboot.org>2016-02-18 01:35:57 +0100
commite8e66f47631c505ab153d8a348058350b9acfe88 (patch)
tree535bc168855923222affbf6bdb06620cbd8fb343 /src/mainboard/google/parrot
parentffc31d07f7839fa72073aae4ddbbd025ac4a7bac (diff)
downloadcoreboot-e8e66f47631c505ab153d8a348058350b9acfe88.tar.xz
southbridge/intel/bd82x6x: Use common gpio.c
Use shared gpio code from common folder. Bd82x6x's gpio.c and gpio.h is used by other southbridges as well and will be removed once it is unused. Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13614 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/parrot')
-rw-r--r--src/mainboard/google/parrot/chromeos.c92
-rw-r--r--src/mainboard/google/parrot/gpio.c2
-rw-r--r--src/mainboard/google/parrot/romstage.c1
3 files changed, 17 insertions, 78 deletions
diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c
index 82198a938d..c898f0e39c 100644
--- a/src/mainboard/google/parrot/chromeos.c
+++ b/src/mainboard/google/parrot/chromeos.c
@@ -21,6 +21,7 @@
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include <ec/compal/ene932/ec.h>
#include "ec.h"
@@ -83,104 +84,41 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_lid_switch(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-
- if (!gpio_base)
- return 0;
-
- u32 gp_lvl = inl(gpio_base + GP_LVL);
- return (gp_lvl >> 15) & 1;
+ return get_gpio(15);
}
int get_developer_mode_switch(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
+ u8 gpio = !get_gpio(17);
+ /*
+ * Dev mode is controlled by EC and uboot stores a flag in TPM.
+ * This GPIO is only for the debug header.
+ * It is AND'd to the EC request.
+ */
- if (!gpio_base)
- return(0);
-
-/*
- * Dev mode is controled by EC and uboot stores a flag in TPM. This GPIO is only
- * for the debug header. It is AND'd to the EC request.
- */
-
- u32 gp_lvl = inl(gpio_base + GP_LVL);
- printk(BIOS_DEBUG,"DEV MODE GPIO 17: %x\n", !((gp_lvl >> 17) & 1));
+ printk(BIOS_DEBUG, "DEV MODE GPIO 17: %x\n", gpio);
/* GPIO17, active low -- return active high reading and let
* it be inverted by the caller if needed. */
- return !((gp_lvl >> 17) & 1);
+ return gpio;
}
int get_write_protect_state(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-
- if (!gpio_base)
- return 0;
-
- u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
-
- return !((gp_lvl3 >> (70 - 64)) & 1);
+ return !get_gpio(70);
}
int get_recovery_mode_switch(void)
{
- u8 rec_mode;
-
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-
- if (!gpio_base)
- return(0);
-
+ u8 gpio = !get_gpio(68);
/* GPIO68, active low. For Servo support
* Treat as active high and let the caller invert if needed. */
- u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
- rec_mode = !((gp_lvl3 >> (68 - 64)) & 1);
- printk(BIOS_DEBUG,"REC MODE GPIO 68: %x\n", rec_mode);
+ printk(BIOS_DEBUG, "REC MODE GPIO 68: %x\n", gpio);
- return (rec_mode);
+ return gpio;
}
int parrot_ec_running_ro(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-
- if (!gpio_base)
- return(0);
-
- /* GPIO68 EC_RW is active low.
- * Treat as active high and let the caller invert if needed. */
- u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
- return !((gp_lvl3 >> (68 - 64)) & 1);
+ return !get_gpio(68);
}
diff --git a/src/mainboard/google/parrot/gpio.c b/src/mainboard/google/parrot/gpio.c
index c3e3e2fbe7..8ad18f1f51 100644
--- a/src/mainboard/google/parrot/gpio.c
+++ b/src/mainboard/google/parrot/gpio.c
@@ -16,7 +16,7 @@
#ifndef PARROT_GPIO_H
#define PARROT_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <southbridge/intel/common/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_NONE, /* NOT USED */
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 5897d13bcf..135cc766f1 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -30,6 +30,7 @@
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h>