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| author | David Hendricks <dhendrix@chromium.org> | 2013-08-29 13:12:56 -0700 |
|---|---|---|
| committer | Isaac Christensen <isaac.christensen@se-eng.com> | 2014-08-12 22:20:23 +0200 |
| commit | 5a0fdb4565dc6baf89155268dd0f52e6885197d8 (patch) | |
| tree | 9e29218f8c95cf5321f39067c798ae405532a973 /src/mainboard/google/pit | |
| parent | 122b6d6ce694cd55087b4956780b2bbde8ccc6fe (diff) | |
| download | coreboot-5a0fdb4565dc6baf89155268dd0f52e6885197d8.tar.xz | |
exynos5420: minor clean-up memory related stuff
This cleans up a few minor things (mostly #defines) of the memory code
for exynos5420, pit, and kirby. Specifically:
- CONCONTROL.empty is read-only, so don't try to set it and also
get rid of the unneeded DMC_CONCONTROL_EMPTY_ENABLE #define.
- MEMBASECONFIG* overlaps members of the mem_timings struct and
are mainboard-dependent anyway, so get rid of 'em.
- DMC_MEMCONTROL_TP_DISABLE corresponds to a reserved bit. It may
have been deprecated.
- Same with TIMING* #defines.
- Clarify DDR_MODE_* usage and use mem->mem_type when appropriate.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ideb21efcc97b24f7e115e90051c20daef4480f17
Reviewed-on: https://chromium-review.googlesource.com/167500
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit 650dba32cb217414c422907398f68e784e5720e8)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6614
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/mainboard/google/pit')
| -rw-r--r-- | src/mainboard/google/pit/memory.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/pit/memory.c b/src/mainboard/google/pit/memory.c index 0c30773bdd..7d8ddcbda6 100644 --- a/src/mainboard/google/pit/memory.c +++ b/src/mainboard/google/pit/memory.c @@ -81,7 +81,6 @@ const struct mem_timings mem_timings = { .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | DMC_MEMCONTROL_DPWRDN_DISABLE | DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | DMC_MEMCONTROL_DSREF_DISABLE | DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | DMC_MEMCONTROL_MEM_TYPE_DDR3 | @@ -107,7 +106,6 @@ const struct mem_timings mem_timings = { .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | DMC_CONCONTROL_TIMEOUT_LEVEL0 | DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | DMC_CONCONTROL_AREF_EN_DISABLE | DMC_CONCONTROL_IO_PD_CON_DISABLE, .dmc_channels = 1, |