diff options
| author | Shelley Chen <shchen@google.com> | 2018-10-26 14:07:16 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-05 09:16:41 +0000 |
| commit | 715cb40963c47250c6d25624a60b65d8f0f237d3 (patch) | |
| tree | 7f714e18f3af2c47b00852a6b34189d03248194e /src/mainboard/google/poppy/variants/nami/devicetree.cb | |
| parent | 0f14df46aa8717097b032c24f8410e0520f5a755 (diff) | |
| download | coreboot-715cb40963c47250c6d25624a60b65d8f0f237d3.tar.xz | |
mb/google/poppy/variants/nami: Enable FP MCU
Some variants of nami will have a fingerprint MCU.
BUG=b:118503113
BRANCH=Nami
TEST=None (build and boot, but no hw yet)
Change-Id: I446dc09cdf7f84a801723cb403d2de80e0997c65
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/poppy/variants/nami/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/poppy/variants/nami/devicetree.cb | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index bd8e4bdd98..de00522f8c 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -277,7 +277,7 @@ chip soc/intel/skylake [PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C5] = PchSerialIoDisabled, [PchSerialIoIndexSpi0] = PchSerialIoPci, - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, + [PchSerialIoIndexSpi1] = PchSerialIoPci, [PchSerialIoIndexUart0] = PchSerialIoPci, [PchSerialIoIndexUart1] = PchSerialIoDisabled, [PchSerialIoIndexUart2] = PchSerialIoSkipInit, @@ -449,7 +449,17 @@ chip soc/intel/skylake device spi 0 on end end end # GSPI #0 - device pci 1e.3 off end # GSPI #1 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D6_IRQ)" + register "wake" = "GPE0_DW1_06" # GPP_D6 + device spi 0 on end + end # FPMCU + end # GSPI #1 device pci 1e.4 on end # eMMC device pci 1e.5 off end # SDIO device pci 1e.6 off end # SDCard |