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authorAngel Pons <th3fanbus@gmail.com>2020-08-03 12:54:48 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-08-04 12:21:14 +0000
commite16692ed07ec5a2deaf9769f4ecc3d65dd21ce1d (patch)
treea3d4794fb34e6f00d9aee3efc04b1a9173928304 /src/mainboard/google/poppy/variants/nautilus/devicetree.cb
parent20245aa622d4224ecd2cdc88438d29f7b5868744 (diff)
downloadcoreboot-e16692ed07ec5a2deaf9769f4ecc3d65dd21ce1d.tar.xz
mb/**/{devicetree,overridetree}.cb: Indent with tabs
Use tabs instead of eight (sometimes less) spaces. Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/google/poppy/variants/nautilus/devicetree.cb')
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/devicetree.cb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 0a67d4d7f9..d64bd8a022 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -144,8 +144,8 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[0]" = "1"
# RP 1 uses SRCCLKREQ1#
register "PcieRpClkReqNumber[0]" = "1"
- # RP 1 uses uses CLK SRC 1
- register "PcieRpClkSrcNumber[0]" = "1"
+ # RP 1 uses uses CLK SRC 1
+ register "PcieRpClkSrcNumber[0]" = "1"
# RP 1, Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[0]" = "1"
# RP 1, Enable Latency Tolerance Reporting Mechanism