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authorSubrata Banik <subrata.banik@intel.com>2018-05-09 14:55:09 +0530
committerSubrata Banik <subrata.banik@intel.com>2018-06-06 06:23:45 +0000
commitc4986eb7f4eee0f305c6a6f05b45effae152062c (patch)
tree46185566d98e49bbfa60acfdedc60e1e423823d3 /src/mainboard/google/poppy/variants/nautilus/devicetree.cb
parentf513cebd8b966c15e3c8abcd2d0f540607ea5964 (diff)
downloadcoreboot-c4986eb7f4eee0f305c6a6f05b45effae152062c.tar.xz
soc/intel/common/block: Add common chip config block
Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/poppy/variants/nautilus/devicetree.cb')
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/devicetree.cb132
1 files changed, 73 insertions, 59 deletions
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 7cf764e755..39d7353f58 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -179,80 +179,97 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
- # Touchscreen
- register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
- register "i2c[0]" = "{
- .speed = I2C_SPEED_FAST,
- .speed_config[0] = {
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
+ #| I2C0 | Touchscreen |
+ #| I2C1 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| I2C2 | Trackpad |
+ #| I2C3 | Pen |
+ #| I2C4 | Camera |
+ #| I2C5 | Audio |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 180,
+ .scl_hcnt = 90,
+ .sda_hold = 36,
+ },
+ },
+ .i2c[1] = {
+ .early_init = 1,
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 185,
+ .scl_hcnt = 90,
+ .sda_hold = 36,
+ },
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 190,
+ .scl_hcnt = 100,
+ .sda_hold = 36,
+ },
+ },
+ .i2c[3] = {
.speed = I2C_SPEED_FAST,
- .scl_lcnt = 180,
- .scl_hcnt = 90,
- .sda_hold = 36,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 185,
+ .scl_hcnt = 90,
+ .sda_hold = 36,
+ },
+ },
+ .i2c[4] = {
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 190,
+ .scl_hcnt = 100,
+ .sda_hold = 36,
+ },
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 190,
+ .scl_hcnt = 100,
+ .sda_hold = 36,
+ },
},
}"
+ # Touch Screen
+ register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
+
# H1
register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"
- # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR
- # for TPM communication before memory is up.
- register "i2c[1]" = "{
- .early_init = 1,
- .speed = I2C_SPEED_FAST,
- .speed_config[0] = {
- .speed = I2C_SPEED_FAST,
- .scl_lcnt = 185,
- .scl_hcnt = 90,
- .sda_hold = 36,
- },
- }"
# Trackpad
register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"
- register "i2c[2]" = "{
- .speed = I2C_SPEED_FAST,
- .speed_config[0] = {
- .speed = I2C_SPEED_FAST,
- .scl_lcnt = 190,
- .scl_hcnt = 100,
- .sda_hold = 36,
- },
- }"
# Pen
register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"
- register "i2c[3]" = "{
- .speed = I2C_SPEED_FAST,
- .speed_config[0] = {
- .speed = I2C_SPEED_FAST,
- .scl_lcnt = 185,
- .scl_hcnt = 90,
- .sda_hold = 36,
- },
- }"
# Camera
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
- register "i2c[4]" = "{
- .speed = I2C_SPEED_FAST,
- .speed_config[0] = {
- .speed = I2C_SPEED_FAST,
- .scl_lcnt = 190,
- .scl_hcnt = 100,
- .sda_hold = 36,
- },
- }"
# Audio
register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8"
- register "i2c[5]" = "{
- .speed = I2C_SPEED_FAST,
- .speed_config[0] = {
- .speed = I2C_SPEED_FAST,
- .scl_lcnt = 190,
- .scl_hcnt = 100,
- .sda_hold = 36,
- },
- }"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
@@ -278,9 +295,6 @@ chip soc/intel/skylake
# Use default SD card detect GPIO configuration
register "sdcard_cd_gpio_default" = "GPP_E15"
- # Lock Down
- register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
-
# PCH Trip Temperature in degree C
register "pch_trip_temp" = "75"