diff options
author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-05-10 01:24:11 +0530 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-18 07:13:23 +0000 |
commit | 97c5464443306f26b61cec3a0f50108a5c06b7ef (patch) | |
tree | f085457907ad200a0d9d9be8a07c937e755fae91 /src/mainboard/google/poppy/variants/nocturne | |
parent | 19c2ce7639d55908d210782ae5a0315396cc7eaf (diff) | |
download | coreboot-97c5464443306f26b61cec3a0f50108a5c06b7ef.tar.xz |
skylake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Skylake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on nami system
Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/poppy/variants/nocturne')
-rw-r--r-- | src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 8 | ||||
-rw-r--r-- | src/mainboard/google/poppy/variants/nocturne/mainboard.c | 5 |
2 files changed, 9 insertions, 4 deletions
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 96fcc39e65..8819350dce 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -66,9 +66,11 @@ chip soc/intel/skylake # Set speed_shift_enable to 1 to enable P-States, and 0 to disable register "speed_shift_enable" = "1" - register "tdp_pl1_override" = "7" - register "tdp_pl2_override" = "18" - register "psys_pmax" = "45" + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 18, + .psys_pmax = 45, + }" register "tcc_offset" = "10" register "pirqa_routing" = "PCH_IRQ11" diff --git a/src/mainboard/google/poppy/variants/nocturne/mainboard.c b/src/mainboard/google/poppy/variants/nocturne/mainboard.c index 8d72144f9b..1482b3458f 100644 --- a/src/mainboard/google/poppy/variants/nocturne/mainboard.c +++ b/src/mainboard/google/poppy/variants/nocturne/mainboard.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <intelblocks/power_limit.h> /* PL2 limit in watts for AML and KBL */ #define PL2_AML 18 @@ -26,8 +27,10 @@ static uint32_t get_pl2(void) /* Override dev tree settings per board */ void variant_devtree_update(void) { + struct soc_power_limits_config *soc_conf; config_t *cfg = config_of_soc(); + soc_conf = &cfg->power_limits_config; /* Update PL2 based on CPU */ - cfg->tdp_pl2_override = get_pl2(); + soc_conf->tdp_pl2_override = get_pl2(); } |