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author | Wisley Chen <wisley.chen@quantatw.com> | 2017-09-01 14:33:06 +0800 |
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committer | Furquan Shaikh <furquan@google.com> | 2017-09-13 19:31:26 +0000 |
commit | f7d0f02b367199603e554fb424164a9a31d67afc (patch) | |
tree | 3ac1b5d9aa6c169612a844f16959bc06f683c4f9 /src/mainboard/google/poppy/variants/soraka/include | |
parent | b92f6d36dfc7f6dc2a9fb0551739feb3dc3ea04c (diff) | |
download | coreboot-f7d0f02b367199603e554fb424164a9a31d67afc.tar.xz |
mb/google/soraka: Update DPTF parameters
Cloned from baseboard/dptf.asl and update the parameters for soraka.
1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.
CPU: passive point:85, critial point:100
TSR0: passive point:55, critial point:65
TSR1: passive point:58, critial point:70
TSR2: passive point:60, critial point:75
TSR3: passive point:60, critial point:75
2. Set PL1 Max to 7W, and PL1 Min 4.5W
3. Change sampling period of thermal relationship table (TRT) setting
CPU: 5 seconds
TSR0: 30 seconds
TSR1: 30 seconds
TSR2: 8 seconds
TSR3: 8 Seconds
BUG=b:65467566
TEST=build, boot on soraka, and verified by thermal team.
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I6af93fa358a037df2088213ee4df5e2cfd047590
Reviewed-on: https://review.coreboot.org/21453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/poppy/variants/soraka/include')
-rw-r--r-- | src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl | 79 |
1 files changed, 77 insertions, 2 deletions
diff --git a/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl index a9ec74269f..b854608857 100644 --- a/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. + * Copyright (C) 2017 Google Inc. + * Copyright (C) 2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,4 +14,78 @@ * GNU General Public License for more details. */ -#include <baseboard/acpi/dptf.asl> +#define DPTF_CPU_PASSIVE 85 +#define DPTF_CPU_CRITICAL 100 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Ambient" +#define DPTF_TSR0_PASSIVE 55 +#define DPTF_TSR0_CRITICAL 65 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "Charger" +#define DPTF_TSR1_PASSIVE 58 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "DRAM" +#define DPTF_TSR2_PASSIVE 60 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_TSR3_SENSOR_ID 4 +#define DPTF_TSR3_SENSOR_NAME "eMMC" +#define DPTF_TSR3_PASSIVE 60 +#define DPTF_TSR3_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 300, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 }, +#endif + + /* CPU Throttle Effect on DRAM (TSR2) */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 80, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on eMMC (TSR3) */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 80, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 4500, /* PowerLimitMinimum */ + 7000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> |