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authorGaggery Tsai <gaggery.tsai@intel.com>2019-04-18 08:54:38 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-04-26 09:20:37 +0000
commit56d66ae854168f65c9cb6181d89f264778f5e76a (patch)
treeaf98e73ae878006e829fdbef6b483b549adcd4cc /src/mainboard/google/poppy/variants
parenta11553dabdfbc4641e3fa73a3c4d0cb8eade2ea1 (diff)
downloadcoreboot-56d66ae854168f65c9cb6181d89f264778f5e76a.tar.xz
mb/google/poppy/variants/atlas: Revise AC/DC loadline
This patch revises the AC/DC loadline settings because some major layout changes between proto and evt boards. BUG=b:130740639 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage and boot to the OS. Change-Id: Iea12c621e7fab427a0de8f43f0290bf01d0c5a09 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com>
Diffstat (limited to 'src/mainboard/google/poppy/variants')
-rw-r--r--src/mainboard/google/poppy/variants/atlas/devicetree.cb18
1 files changed, 9 insertions, 9 deletions
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 53af87d49e..ad79bcab0e 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -88,8 +88,8 @@ chip soc/intel/skylake
#| ImonOffset | 0 | 0 | 0 | 0 |
#| IccMax | set by SoC code per CPU SKU |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
- #| AcLoadline | 14.75 | 4.42 | 4.7 | 4.7 |
- #| DcLoadline | 14.2 | 4.2 | 4.41 | 4.41 |
+ #| AcLoadline | 16.20 | 5.24 | 4.62 | 4.62 |
+ #| DcLoadline | 14.2 | 4.94 | 4.25 | 4.25 |
#+----------------+-------+-------+-------+-------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1,
@@ -101,7 +101,7 @@ chip soc/intel/skylake
.imon_slope = 0x0,
.imon_offset = 0x0,
.voltage_limit = 1520,
- .ac_loadline = 1475,
+ .ac_loadline = 1620,
.dc_loadline = 1420,
}"
@@ -115,8 +115,8 @@ chip soc/intel/skylake
.imon_slope = 0x0,
.imon_offset = 0x0,
.voltage_limit = 1520,
- .ac_loadline = 442,
- .dc_loadline = 420,
+ .ac_loadline = 524,
+ .dc_loadline = 494,
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
@@ -129,8 +129,8 @@ chip soc/intel/skylake
.imon_slope = 0x0,
.imon_offset = 0x0,
.voltage_limit = 1520,
- .ac_loadline = 470,
- .dc_loadline = 441,
+ .ac_loadline = 462,
+ .dc_loadline = 425,
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
@@ -143,8 +143,8 @@ chip soc/intel/skylake
.imon_slope = 0x0,
.imon_offset = 0x0,
.voltage_limit = 1520,
- .ac_loadline = 470,
- .dc_loadline = 441,
+ .ac_loadline = 462,
+ .dc_loadline = 425,
}"
# PCIe Root port 1 with SRCCLKREQ1# (WLAN)