diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-07-20 15:37:05 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-07-22 05:25:01 +0000 |
| commit | 4a1d450d07de5ac94ede8a61a1233e3ae675133d (patch) | |
| tree | e45052bdb355409b83f9d2db618572f3dc4b7c3a /src/mainboard/google/poppy | |
| parent | 907a0cfc305e0f02e19954dd509b4ed8df564f76 (diff) | |
| download | coreboot-4a1d450d07de5ac94ede8a61a1233e3ae675133d.tar.xz | |
mainboard/google/poppy/variants/soraka: Update GPP_{D1,D2,B7} config
GPP_B7, GPP_D1 and GPP_D2 are not used going forward. Mark them as NC
in gpio table.
BUG=b:62322846,b:62240755
Change-Id: I7aee08314e6ce96d5913ae315bf75f5c04ab7370
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20672
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/poppy')
| -rw-r--r-- | src/mainboard/google/poppy/variants/soraka/gpio.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c index 2189b6c400..2a922a92e9 100644 --- a/src/mainboard/google/poppy/variants/soraka/gpio.c +++ b/src/mainboard/google/poppy/variants/soraka/gpio.c @@ -76,8 +76,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NC(GPP_B5), /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), - /* B7 : SRCCLKREQ2# ==> WWAN_PCIE_CLKREQ_L */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B7 : SRCCLKREQ2# ==> NC */ + PAD_CFG_NC(GPP_B7), /* B8 : SRCCLKREQ3# ==> NC */ PAD_CFG_NC(GPP_B8), /* B9 : SRCCLKREQ4# ==> NC */ @@ -180,10 +180,10 @@ static const struct pad_config gpio_table[] = { /* D0 : SPI1_CS# ==> NC */ PAD_CFG_NC(GPP_D0), - /* D1 : SPI1_CLK ==> PEN_IRQ_L */ - PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), - /* D2 : SPI1_MISO ==> PEN_PDCT_L */ - PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D1 : SPI1_CLK ==> NC */ + PAD_CFG_NC(GPP_D1), + /* D2 : SPI1_MISO ==> NC */ + PAD_CFG_NC(GPP_D2), /* D3 : SPI1_MOSI ==> NC */ PAD_CFG_NC(GPP_D3), /* D4 : FASHTRIG ==> NC */ |