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authorMatt Delco <delco@chromium.org>2018-08-15 11:55:26 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-08-20 15:54:28 +0000
commitc1cb6da81600f6ef71f114fc6bc56c90b090462d (patch)
tree317334bff07f51bf6291829b68ffb623cf70029d /src/mainboard/google/poppy
parent1950ed9ee3baaf3ecfd3fb2583bfdce562395cb7 (diff)
downloadcoreboot-c1cb6da81600f6ef71f114fc6bc56c90b090462d.tar.xz
mb/google/poppy/variants/nocturne: enable eist
Enable Enhanced Intel SpeedStep (EIST) on nocturne. Change-Id: Ie9b832f5bc3a5ef300783bd9bcd7cf5d186b98fa Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/poppy')
-rw-r--r--src/mainboard/google/poppy/variants/nocturne/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index f81d43d1f2..a6988fa4ec 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -7,6 +7,8 @@ chip soc/intel/skylake
register "deep_s5_enable_dc" = "1"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
+ register "eist_enable" = "1"
+
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE