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authorAngel Pons <th3fanbus@gmail.com>2020-08-03 12:54:48 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-08-04 12:21:14 +0000
commite16692ed07ec5a2deaf9769f4ecc3d65dd21ce1d (patch)
treea3d4794fb34e6f00d9aee3efc04b1a9173928304 /src/mainboard/google/poppy
parent20245aa622d4224ecd2cdc88438d29f7b5868744 (diff)
downloadcoreboot-e16692ed07ec5a2deaf9769f4ecc3d65dd21ce1d.tar.xz
mb/**/{devicetree,overridetree}.cb: Indent with tabs
Use tabs instead of eight (sometimes less) spaces. Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/google/poppy')
-rw-r--r--src/mainboard/google/poppy/variants/nami/devicetree.cb14
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/devicetree.cb4
-rw-r--r--src/mainboard/google/poppy/variants/nocturne/devicetree.cb38
3 files changed, 28 insertions, 28 deletions
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 8e1f954d8a..bf3b7bd923 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -366,19 +366,19 @@ chip soc/intel/skylake
end
end # I2C #1
device pci 15.2 on
- chip drivers/i2c/hid
- register "generic.hid" = ""WCOM005C""
- register "generic.desc" = ""WCOM Digitizer""
- register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)"
+ chip drivers/i2c/hid
+ register "generic.hid" = ""WCOM005C""
+ register "generic.desc" = ""WCOM Digitizer""
+ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)"
register "generic.probed" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D3)"
register "generic.reset_delay_ms" = "20"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "generic.wake" = "GPE0_DW2_01"
- register "hid_desc_reg_offset" = "0x1"
- device i2c 0x9 on end
- end
+ register "hid_desc_reg_offset" = "0x1"
+ device i2c 0x9 on end
+ end
chip drivers/generic/gpio_keys
register "name" = ""PENH""
register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_E8)"
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 0a67d4d7f9..d64bd8a022 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -144,8 +144,8 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[0]" = "1"
# RP 1 uses SRCCLKREQ1#
register "PcieRpClkReqNumber[0]" = "1"
- # RP 1 uses uses CLK SRC 1
- register "PcieRpClkSrcNumber[0]" = "1"
+ # RP 1 uses uses CLK SRC 1
+ register "PcieRpClkSrcNumber[0]" = "1"
# RP 1, Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[0]" = "1"
# RP 1, Enable Latency Tolerance Reporting Mechanism
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 8959a2902e..26207f529e 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -147,19 +147,19 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
- # Root port 9 (x2)
- # PcieRpEnable: Enable root port
- # PcieRpClkReqSupport: Enable CLKREQ#
- # PcieRpClkReqNumber: Uses SRCCLKREQ2#
- # PcieRpClkSrcNumber: Uses 3
- # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
- # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism
- register "PcieRpEnable[8]" = "1"
- register "PcieRpClkReqSupport[8]" = "1"
- register "PcieRpClkReqNumber[8]" = "2"
- register "PcieRpClkSrcNumber[8]" = "3"
- register "PcieRpAdvancedErrorReporting[8]" = "1"
- register "PcieRpLtrEnable[8]" = "1"
+ # Root port 9 (x2)
+ # PcieRpEnable: Enable root port
+ # PcieRpClkReqSupport: Enable CLKREQ#
+ # PcieRpClkReqNumber: Uses SRCCLKREQ2#
+ # PcieRpClkSrcNumber: Uses 3
+ # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
+ # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpClkReqSupport[8]" = "1"
+ register "PcieRpClkReqNumber[8]" = "2"
+ register "PcieRpClkSrcNumber[8]" = "3"
+ register "PcieRpAdvancedErrorReporting[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
# USB 2.0
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
@@ -306,12 +306,12 @@ chip soc/intel/skylake
register "generic.desc" = ""WCOM Digitizer""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
register "generic.speed" = "I2C_SPEED_FAST_PLUS"
- register "generic.probed" = "1"
- register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)"
- register "generic.reset_delay_ms" = "20"
- register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)"
- register "generic.enable_delay_ms" = "1"
- register "generic.has_power_resource" = "1"
+ register "generic.probed" = "1"
+ register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)"
+ register "generic.reset_delay_ms" = "20"
+ register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)"
+ register "generic.enable_delay_ms" = "1"
+ register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x1"
device i2c 0a on end