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| author | Matt DeVillier <matt.devillier@gmail.com> | 2017-01-12 12:19:21 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-17 17:57:40 +0100 |
| commit | ce0a56419854d8c2bd0fac401c76139106fc4dd8 (patch) | |
| tree | a6c090fddb240f383de2ad65769a7017e2f530bf /src/mainboard/google/rambi/acpi/dptf.asl | |
| parent | e7dbeaeac3f9e37625a5b4cda04e67597972e4ee (diff) | |
| download | coreboot-ce0a56419854d8c2bd0fac401c76139106fc4dd8.tar.xz | |
Combine Baytrail ChromeOS devices using variant scheme
Combine existing boards google/enguarde and google/ninja using
their common reference board google/rambi as a baseboard.
Variants contain board specific data:
- DPTF ACPI components
- I2C ACPI devices
- RAM config / SPD data
- devicetree config
- GPIOs
- board-specific HW components (e.g., LAN)
Additionally, some minor cleanup/changes were made:
- remove unused ACPI trackpad/touchscreen devices
- correct I2C addresses in SMBIOS entries
- clean up comment formatting
- remove ACPI device for unused light sensor
- switch I2C ACPI devices from edge to level triggered interrupts,
for better compatibility/functionality (and to be consistent
with other recently-upstreamed ChromeOS devices)
The existing enguarde and ninja boards are removed.
Variant setup modeled after google/auron
Change-Id: Iae7855af9a224fd4cb948b854494e39b545ad449
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18129
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/rambi/acpi/dptf.asl')
| -rw-r--r-- | src/mainboard/google/rambi/acpi/dptf.asl | 32 |
1 files changed, 3 insertions, 29 deletions
diff --git a/src/mainboard/google/rambi/acpi/dptf.asl b/src/mainboard/google/rambi/acpi/dptf.asl index 0b79aadb7b..673ad1c1ae 100644 --- a/src/mainboard/google/rambi/acpi/dptf.asl +++ b/src/mainboard/google/rambi/acpi/dptf.asl @@ -11,34 +11,8 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 80 -#define DPTF_CPU_CRITICAL 90 - -#define DPTF_TSR0_SENSOR_ID 1 -#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 48 -#define DPTF_TSR0_CRITICAL 70 - -#define DPTF_TSR1_SENSOR_ID 2 -#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 60 -#define DPTF_TSR1_CRITICAL 70 - -#define DPTF_TSR2_SENSOR_ID 3 -#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 70 - -#define DPTF_ENABLE_CHARGER - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ - Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ -}) +/* Include variant DPTF */ +#include <variant/acpi/dptf.asl> /* Mainboard specific _PDL is 1GHz */ Name (MPDL, 8) @@ -83,5 +57,5 @@ Name (MPPC, Package () } }) -/* Include Baytrail DPTF */ +/* Include SoC DPTF */ #include <soc/intel/baytrail/acpi/dptf/dptf.asl> |