diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-10-04 16:00:07 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-02-05 05:24:26 +0100 |
| commit | c625d0983c6427277c3f6ebd9911def76d6351c9 (patch) | |
| tree | 25057244d5a367bb84f2f7320267be4bb2ea9474 /src/mainboard/google/rambi/dsdt.asl | |
| parent | 189aa3e2aec9ca6446d8425a3ec3a11cb4b5c696 (diff) | |
| download | coreboot-c625d0983c6427277c3f6ebd9911def76d6351c9.tar.xz | |
mainboard/google: add initial rambi mainboard support
BUG=chrome-os-partner:23121
BRANCH=None
TEST=None
Change-Id: I283415be326e2d92e1e1bf7866954f17a7266edb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171940
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-on: http://review.coreboot.org/4865
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/google/rambi/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/rambi/dsdt.asl | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl new file mode 100644 index 0000000000..172aaf46fb --- /dev/null +++ b/src/mainboard/google/rambi/dsdt.asl @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ENABLE_TPM + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/baytrail/acpi/globalnvs.asl> + + //#include "acpi/thermal.asl" + + //#include <soc/intel/baytrail/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + //#include <soc/intel/baytrail/acpi/northcluster.asl> + #include <soc/intel/baytrail/acpi/southcluster.asl> + } + } + + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <soc/intel/baytrail/acpi/sleepstates.asl> +} |