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| author | Aaron Durbin <adurbin@chromium.org> | 2013-11-11 14:45:27 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-05-06 18:39:29 +0200 |
| commit | 9f83e873f4f0a06a68f68414720e837a69f54184 (patch) | |
| tree | 657110cd0bf78d5106502436c87ec2a5ba245da6 /src/mainboard/google/rambi/ec.c | |
| parent | 59a4cd55782f1148d37f0c2408657ba93deefc86 (diff) | |
| download | coreboot-9f83e873f4f0a06a68f68414720e837a69f54184.tar.xz | |
baytrail: add GPIO SMI support
GPIOs which trigger SMIs only set the status bits in the ALT_GPIO_SMI
regier. No bits in the SMI_STS register are set. Therefore, the
ALT_GPIO_SMI register needs to be read and cleared on every SMI.
Additionally, the mainboard_gpi_smi() handler needs to be called as
well on every SMI because of this property.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted to recovery screen. Typed 'lidclose' on EC
console. SMI occurred which caused the board to be shutdown.
Change-Id: Ic204d8b928a0cb4f51f108a649f374d9f94e4f47
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176391
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4958
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/google/rambi/ec.c')
0 files changed, 0 insertions, 0 deletions