diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-10-08 15:33:39 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-02-11 22:20:28 +0100 |
| commit | 1f5eb1f78e839a5dc1454c20060ccca14a74deb5 (patch) | |
| tree | 0b3147028a2c636580ff58ea9b20d2797605ab91 /src/mainboard/google/rambi/romstage.c | |
| parent | 5f8ad56358b04ba0b0752944d2ed643d4df9c480 (diff) | |
| download | coreboot-1f5eb1f78e839a5dc1454c20060ccca14a74deb5.tar.xz | |
rambi: add per-sku SPD support
There are currently 4 SKUs:
0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz
Add each of the 4 spds to the build, and use the proper
parameters to MRC to use the in-memory SPD information.
BUG=chrome-os-partner:22865
BRANCH=None
TEST=Built. Noted 1024 bytes of SPD content.
Change-Id: Ife96650f9b0032b6bd0d1bdd63b8970e29868365
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172280
Reviewed-on: http://review.coreboot.org/4872
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/google/rambi/romstage.c')
| -rw-r--r-- | src/mainboard/google/rambi/romstage.c | 45 |
1 files changed, 43 insertions, 2 deletions
diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index f8451731b8..d15a21dc2d 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -19,19 +19,60 @@ #include <stdint.h> #include <string.h> +#include <cbfs.h> #include <console/console.h> +#include <baytrail/gpio.h> #include <baytrail/mrc_wrapper.h> #include <baytrail/romstage.h> +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + */ +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +static void *get_spd_pointer(char *spd_file_content, int total_spds) +{ + int ram_id = 0; + + ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0); + ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1); + ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2); + + if (ram_id >= total_spds) + return NULL; + + return &spd_file_content[SPD_SIZE * ram_id]; +} + void mainboard_romstage_entry(struct romstage_params *rp) { + struct cbfs_file *spd_file; + void *spd_content; + struct mrc_params mp = { .mainboard = { .dram_type = DRAM_DDR3L, - .dram_info_location = DRAM_INFO_SPD_SMBUS, - .spd_addrs = { 0xa0, 0xa2 }, + .dram_info_location = DRAM_INFO_SPD_MEM, }, }; + + spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + if (!spd_file) + die("SPD data not found."); + + /* Both channels are always present. */ + spd_content = get_spd_pointer(CBFS_SUBHEADER(spd_file), + ntohl(spd_file->len) / SPD_SIZE); + mp.mainboard.dram_data[0] = spd_content; + mp.mainboard.dram_data[1] = spd_content; + rp->mrc_params = ∓ romstage_common(rp); } |