diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-08-01 13:05:14 -0500 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2018-08-01 22:23:54 +0000 |
| commit | 3044af7adc652f41670f8de0c3c54bc09f632079 (patch) | |
| tree | f1b936af303292c7e3ed35a188809fbc3f9a249a /src/mainboard/google/rambi/variants | |
| parent | 9fe248fbeca2c62153dc4d8d89bfc9cd1d84dcd3 (diff) | |
| download | coreboot-3044af7adc652f41670f8de0c3c54bc09f632079.tar.xz | |
mb/google,samsung/*: Add LPC TPM chip driver to devicetree
With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code]
and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing
TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver
(drivers/pc80/tpm) must be added to devicetree in order to ensure the
new acpigen code is used to replace it.
Test: boot various google/samsung boards, verify SSDT created with
LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux
Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27786
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/rambi/variants')
16 files changed, 48 insertions, 0 deletions
diff --git a/src/mainboard/google/rambi/variants/banjo/devicetree.cb b/src/mainboard/google/rambi/variants/banjo/devicetree.cb index e380920e0e..acfb2719b4 100644 --- a/src/mainboard/google/rambi/variants/banjo/devicetree.cb +++ b/src/mainboard/google/rambi/variants/banjo/devicetree.cb @@ -88,6 +88,9 @@ chip soc/intel/baytrail device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/candy/devicetree.cb b/src/mainboard/google/rambi/variants/candy/devicetree.cb index 5cbb974cb2..e4a39e9276 100644 --- a/src/mainboard/google/rambi/variants/candy/devicetree.cb +++ b/src/mainboard/google/rambi/variants/candy/devicetree.cb @@ -89,6 +89,9 @@ chip soc/intel/baytrail device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/clapper/devicetree.cb b/src/mainboard/google/rambi/variants/clapper/devicetree.cb index 13902b009b..497a0b1dea 100644 --- a/src/mainboard/google/rambi/variants/clapper/devicetree.cb +++ b/src/mainboard/google/rambi/variants/clapper/devicetree.cb @@ -76,6 +76,9 @@ chip soc/intel/baytrail device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/enguarde/devicetree.cb b/src/mainboard/google/rambi/variants/enguarde/devicetree.cb index 89929b0c6a..3b00bb789e 100644 --- a/src/mainboard/google/rambi/variants/enguarde/devicetree.cb +++ b/src/mainboard/google/rambi/variants/enguarde/devicetree.cb @@ -88,6 +88,9 @@ chip soc/intel/baytrail device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/glimmer/devicetree.cb b/src/mainboard/google/rambi/variants/glimmer/devicetree.cb index 5148225472..db26366b3a 100644 --- a/src/mainboard/google/rambi/variants/glimmer/devicetree.cb +++ b/src/mainboard/google/rambi/variants/glimmer/devicetree.cb @@ -85,6 +85,9 @@ chip soc/intel/baytrail device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/gnawty/devicetree.cb b/src/mainboard/google/rambi/variants/gnawty/devicetree.cb index 0024679eff..30320ccd1f 100644 --- a/src/mainboard/google/rambi/variants/gnawty/devicetree.cb +++ b/src/mainboard/google/rambi/variants/gnawty/devicetree.cb @@ -88,6 +88,9 @@ chip soc/intel/baytrail device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/heli/devicetree.cb b/src/mainboard/google/rambi/variants/heli/devicetree.cb index 8b3c83f588..c3ec601a6c 100644 --- a/src/mainboard/google/rambi/variants/heli/devicetree.cb +++ b/src/mainboard/google/rambi/variants/heli/devicetree.cb @@ -89,6 +89,9 @@ chip soc/intel/baytrail device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/kip/devicetree.cb b/src/mainboard/google/rambi/variants/kip/devicetree.cb index d1d6beb155..5bb99f0483 100644 --- a/src/mainboard/google/rambi/variants/kip/devicetree.cb +++ b/src/mainboard/google/rambi/variants/kip/devicetree.cb @@ -88,6 +88,9 @@ chip soc/intel/baytrail device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/ninja/devicetree.cb b/src/mainboard/google/rambi/variants/ninja/devicetree.cb index 5c9595c49c..c983681378 100644 --- a/src/mainboard/google/rambi/variants/ninja/devicetree.cb +++ b/src/mainboard/google/rambi/variants/ninja/devicetree.cb @@ -89,6 +89,9 @@ chip soc/intel/baytrail device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/orco/devicetree.cb b/src/mainboard/google/rambi/variants/orco/devicetree.cb index 829179462f..63b60979fe 100644 --- a/src/mainboard/google/rambi/variants/orco/devicetree.cb +++ b/src/mainboard/google/rambi/variants/orco/devicetree.cb @@ -88,6 +88,9 @@ chip soc/intel/baytrail device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/quawks/devicetree.cb b/src/mainboard/google/rambi/variants/quawks/devicetree.cb index 320b59bfe4..0e1f7895f1 100644 --- a/src/mainboard/google/rambi/variants/quawks/devicetree.cb +++ b/src/mainboard/google/rambi/variants/quawks/devicetree.cb @@ -85,6 +85,9 @@ chip soc/intel/baytrail device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/rambi/devicetree.cb b/src/mainboard/google/rambi/variants/rambi/devicetree.cb index ddd1914d9e..a24bd33611 100644 --- a/src/mainboard/google/rambi/variants/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/variants/rambi/devicetree.cb @@ -89,6 +89,9 @@ chip soc/intel/baytrail device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/squawks/devicetree.cb b/src/mainboard/google/rambi/variants/squawks/devicetree.cb index 46f2385082..ae4bfe5103 100644 --- a/src/mainboard/google/rambi/variants/squawks/devicetree.cb +++ b/src/mainboard/google/rambi/variants/squawks/devicetree.cb @@ -85,6 +85,9 @@ chip soc/intel/baytrail device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/sumo/devicetree.cb b/src/mainboard/google/rambi/variants/sumo/devicetree.cb index 89e2f2b073..f354815077 100644 --- a/src/mainboard/google/rambi/variants/sumo/devicetree.cb +++ b/src/mainboard/google/rambi/variants/sumo/devicetree.cb @@ -89,6 +89,9 @@ chip soc/intel/baytrail device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/swanky/devicetree.cb b/src/mainboard/google/rambi/variants/swanky/devicetree.cb index db21bd66b1..d591e3fb6a 100644 --- a/src/mainboard/google/rambi/variants/swanky/devicetree.cb +++ b/src/mainboard/google/rambi/variants/swanky/devicetree.cb @@ -88,6 +88,9 @@ chip soc/intel/baytrail device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/rambi/variants/winky/devicetree.cb b/src/mainboard/google/rambi/variants/winky/devicetree.cb index 6d52b89e48..9c25d1eb67 100644 --- a/src/mainboard/google/rambi/variants/winky/devicetree.cb +++ b/src/mainboard/google/rambi/variants/winky/devicetree.cb @@ -89,6 +89,9 @@ chip soc/intel/baytrail device pci 1e.4 off end # HSUART2 device pci 1e.5 off end # SPI device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the |