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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-16 17:37:48 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-28 22:49:27 +0000
commit3e7727908c3137442742a96079def34bb966faaf (patch)
treedb04b88af27e0c76e4ea43892794710fb4fd2148 /src/mainboard/google/rambi
parent81100bf7ff62c4ee53214afb82f2fa9112d109b6 (diff)
downloadcoreboot-3e7727908c3137442742a96079def34bb966faaf.tar.xz
google/rambi,intel/baytrail: Simplified romstage flow
Change-Id: I99440539d7b7586df66395776dcd0b4f72f66818 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34964 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/rambi')
-rw-r--r--src/mainboard/google/rambi/romstage.c22
1 files changed, 8 insertions, 14 deletions
diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c
index 9fbe1ca10e..f74d77d3f3 100644
--- a/src/mainboard/google/rambi/romstage.c
+++ b/src/mainboard/google/rambi/romstage.c
@@ -55,21 +55,13 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
return &spd_file_content[SPD_SIZE * ram_id];
}
-void mainboard_romstage_entry_rp(struct romstage_params *rp)
+void mainboard_fill_mrc_params(struct mrc_params *mp)
{
void *spd_content;
int dual_channel = 0;
void *spd_file;
size_t spd_fsize;
- struct mrc_params mp = {
- .mainboard = {
- .dram_type = DRAM_DDR3L,
- .dram_info_location = DRAM_INFO_SPD_MEM,
- .weaker_odt_settings = 1,
- },
- };
-
spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
&spd_fsize);
if (!spd_file)
@@ -77,10 +69,12 @@ void mainboard_romstage_entry_rp(struct romstage_params *rp)
spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE,
&dual_channel);
- mp.mainboard.dram_data[0] = spd_content;
- if (dual_channel)
- mp.mainboard.dram_data[1] = spd_content;
- rp->mrc_params = &mp;
- romstage_common(rp);
+ mp->mainboard.dram_type = DRAM_DDR3L;
+ mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM,
+ mp->mainboard.weaker_odt_settings = 1,
+
+ mp->mainboard.dram_data[0] = spd_content;
+ if (dual_channel)
+ mp->mainboard.dram_data[1] = spd_content;
}