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authorMate Kukri <kukri.mate@gmail.com>2020-07-03 14:44:49 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-07-12 19:44:02 +0000
commit45b51e01802cbe166ee29c2e27814b9c0ef49c51 (patch)
tree38bd6becb9cc0cd52699ee3ddfbecbdd32c01b67 /src/mainboard/google/rambi
parent355d1c9870555f53db2bd3aa4124d25320320dbc (diff)
downloadcoreboot-45b51e01802cbe166ee29c2e27814b9c0ef49c51.tar.xz
soc/intel/baytrail: Add dedicated devices for MMC and MMC 4.5 controller
- Correctly detect device 17h as the MMC 4.5 controller - Support detection of the "old" MMC controller at device 10h Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Change-Id: I9f0007b1cf01df09f775c088397c3b9c846908c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/google/rambi')
-rw-r--r--src/mainboard/google/rambi/devicetree.cb3
-rw-r--r--src/mainboard/google/rambi/irqroute.h28
2 files changed, 16 insertions, 15 deletions
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index c7bc0b66f2..1ebf1e8e3d 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -59,12 +59,13 @@ chip soc/intel/baytrail
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
+ device pci 10.0 off end # MMC
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
+ device pci 17.0 on end # MMC45
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h
index b5c4f731ff..a4ec620174 100644
--- a/src/mainboard/google/rambi/irqroute.h
+++ b/src/mainboard/google/rambi/irqroute.h
@@ -5,20 +5,20 @@
#include <soc/pm.h>
#define PCI_DEV_PIRQ_ROUTES \
- PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \
- PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \
- PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \
- PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
+ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \
+ PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(MMC45_DEV, D, E, F, G), \
+ PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \
+ PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
#define PIRQ_PIC_ROUTES \
PIRQ_PIC(A, DISABLE), \