baytrail/rambi: S3 support and other updates

baytrail: Change all GPIO related pull resistors from 10K to 20K
Reviewed-on: https://chromium-review.googlesource.com/187570
(cherry picked from commit 762e99861dd1ae61ddcf1ebdec8e698ede54405e)

baytrail: workaround kernel using serial console on resume
Reviewed-on: https://chromium-review.googlesource.com/188011
(cherry picked from commit b0da3bdb5b6b417ad6cab0084359d4eae1cb4469)

baytrail: allow dirty cache line evictions for SMRAM to stick
Reviewed-on: https://chromium-review.googlesource.com/188015
(cherry picked from commit 50fb1e6a844e1db05574c92625da23777ad7a0ca)

baytrail: Optionally pull up TDO and TMS to avoid power loss in S3.
Reviewed-on: https://chromium-review.googlesource.com/188260
(cherry picked from commit e240856609b4eed5ed44ec4e021ed385965768d6)

rambi: always load option rom
Reviewed-on: https://chromium-review.googlesource.com/188721
(cherry picked from commit d8a1d108548d20755f8683497c215e76d513b7a9)

baytrail: use new chromeos ram oops API
Reviewed-on: https://chromium-review.googlesource.com/186394
(cherry picked from commit f38e6969df9b5453b10d49be60b5d033d38b4594)

rambi: always show dev/rec screens on eDP connected panel
Reviewed-on: https://chromium-review.googlesource.com/188731
(cherry picked from commit 7d8570ac52f68492a2250fa536d55f7cbbd9ef95)

baytrail: stop e820 reserving default SMM region
Reviewed-on: https://chromium-review.googlesource.com/189084
(cherry picked from commit 6fce823512f5db5a09a9c89048334c3524c69a24)

baytrai: update MRC wrapper header
Reviewed-on: https://chromium-review.googlesource.com/189196
(cherry picked from commit 36b33a25b6603b6a74990b00d981226440b68970)

rambi: Put LPE device into ACPI mode
Reviewed-on: https://chromium-review.googlesource.com/189371
(cherry picked from commit 5955350cd57fd1b3732b6db62911d824712a5413)

baytrail: DPTF: Enable mainboard-specific PPCC
Reviewed-on: https://chromium-review.googlesource.com/189576
(cherry picked from commit 27fae3e670244b529b7c0241742fc2b55d52c612)

baytrail: Add config option for PCIe wake
Reviewed-on: https://chromium-review.googlesource.com/189994
(cherry picked from commit 1cc31a7c021ec84311f1d4e89dd3e57ca8801ab5)

rambi: Enable PCIe wake
Reviewed-on: https://chromium-review.googlesource.com/189995
(cherry picked from commit c98ae1fee54cfb2b3d3c21a19cdbbf56a0bfa1e6)

Squashed 13 commits for baytrail/rambi.

Change-Id: I153ef5a43e2bede05cfd624f53e24a0013fd8fb4
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6957
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

4 files changed, 31 insertions, 5 deletions

diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig
index f784aedae7..e3f5befeb2 100644
--- a/src/mainboard/google/rambi/Kconfig
+++ b/src/mainboard/google/rambi/Kconfig
@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_RESUME
 	select MAINBOARD_HAS_CHROMEOS
+	select ALWAYS_LOAD_OPROM
 
 config VBOOT_RAMSTAGE_INDEX
 	hex
diff --git a/src/mainboard/google/rambi/acpi/dptf.asl b/src/mainboard/google/rambi/acpi/dptf.asl
index 975c9396f1..507b7c686f 100644
--- a/src/mainboard/google/rambi/acpi/dptf.asl
+++ b/src/mainboard/google/rambi/acpi/dptf.asl
@@ -49,5 +49,26 @@ Name (DTRT, Package () {
 	Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
 })
 
+Name (MPPC, Package ()
+{
+	0x2,		// Revision
+	Package () {	// Power Limit 1
+		0,	// PowerLimitIndex, 0 for Power Limit 1
+		1600,	// PowerLimitMinimum
+		6200,	// PowerLimitMaximum
+		1000,	// TimeWindowMinimum
+		1000,	// TimeWindowMaximum
+		200	// StepSize
+	},
+	Package () {	// Power Limit 2
+		1,	// PowerLimitIndex, 1 for Power Limit 2
+		8000,	// PowerLimitMinimum
+		8000,	// PowerLimitMaximum
+		1000,	// TimeWindowMinimum
+		1000,	// TimeWindowMaximum
+		1000	// StepSize
+	}
+})
+
 /* Include Baytrail DPTF */
 #include <soc/intel/baytrail/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index 95b2b3a398..5d9eec535e 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -32,8 +32,12 @@ chip soc/intel/baytrail
 	register "sdcard_cap_high" = "0x0"
 
 	# Enable devices in ACPI mode
-	register "scc_acpi_mode" = "1"
+	register "lpe_acpi_mode" = "1"
 	register "lpss_acpi_mode" = "1"
+	register "scc_acpi_mode" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
 
 	# Enable PIPEA as DP_C
 	register "gpu_pipea_hotplug" = "6"		# 6ms Pulse
diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c
index f8c80aef9d..19579fb0b7 100644
--- a/src/mainboard/google/rambi/mainboard.c
+++ b/src/mainboard/google/rambi/mainboard.c
@@ -67,15 +67,15 @@ static int int15_handler(void)
 		 * Boot Display Device Hook:
 		 *  bit 0 = CRT
 		 *  bit 1 = TV (eDP) *
-		 *  bit 2 = EFP *
+		 *  bit 2 = EFP
 		 *  bit 3 = LFP
 		 *  bit 4 = CRT2
-		 *  bit 5 = TV2 (eDP) *
-		 *  bit 6 = EFP2 *
+		 *  bit 5 = TV2 (eDP)
+		 *  bit 6 = EFP2
 		 *  bit 7 = LFP2
 		 */
 		X86_AX = 0x005f;
-		X86_CX = 0x0006;
+		X86_CX = 0x0002;
 		res = 1;
 		break;
 	case 0x5f51: