diff options
| author | Shaunak Saha <shaunak.saha@intel.com> | 2016-07-12 16:03:29 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-31 18:57:23 +0200 |
| commit | 57f221e6c47261e82bc21f6baa25dfa17b097f5a (patch) | |
| tree | 3bc4926789db4301d243de537ae83d4cf28fcce4 /src/mainboard/google/reef/devicetree.cb | |
| parent | c663a1f033368dc78131dc615bd310b9820d55f1 (diff) | |
| download | coreboot-57f221e6c47261e82bc21f6baa25dfa17b097f5a.tar.xz | |
google/reef: Enable DPTF in mainboard
This patch enables DPTF support for Google Reef
platform, adds the ASL settings specific to Reef
boards.
BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
under /sys/class/thermal in Reef boards. Navigate to
/sys/class/thermal, and verify that a thermal
zone of type TCPU exists there.
Change-Id: Ib43e4e9dd0d92fffc1b2c8459c552acd04ca0150
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15640
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google/reef/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/reef/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index 02a438468a..5e68d3720c 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -31,6 +31,9 @@ chip soc/intel/apollolake # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for HS200 register "emmc_rx_cmd_data_cntl2" = "0x1001C" + # Enable DPTF + register "dptf_enable" = "1" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route, i.e., if this route changes then the affected GPE |