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author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2016-12-09 11:42:05 +0800 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-12-12 17:51:36 +0100 |
commit | a0f6f9bdbc609e60b64a9d1551006c4cffedc977 (patch) | |
tree | 6247a358836420390a0b45e44b5987bfae632a30 /src/mainboard/google/reef/variants/pyro/devicetree.cb | |
parent | 8d49d52ae930de51633c6533f61a710235399dad (diff) | |
download | coreboot-a0f6f9bdbc609e60b64a9d1551006c4cffedc977.tar.xz |
google/pyro: Set PL2 override to 15000mW
This patch sets PL2 override value to 15W in RAPL registers
and sets DPTF PL2 Max to 15W
BUG=none
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: Ibadf0fa442f556d018c249b1cf88e29c4d57c97f
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17779
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/reef/variants/pyro/devicetree.cb')
-rw-r--r-- | src/mainboard/google/reef/variants/pyro/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index b5e050ea4f..bc06bbba11 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -53,6 +53,8 @@ chip soc/intel/apollolake # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 12W. register "tdp_pl1_override_mw" = "12000" + # Set RAPL PL2 to 15W. + register "tdp_pl2_override_mw" = "15000" # Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" |