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| author | Katherine Hsieh <Katherine.Hsieh@quantatw.com> | 2018-02-27 20:23:53 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-03-01 16:22:21 +0000 |
| commit | aef0d6b0a7ec867ee29acf9e1c695be27626f239 (patch) | |
| tree | 9e741638eb1a38fdaebd9cef11541a2948f766b9 /src/mainboard/google/reef | |
| parent | 0f49bbceef3ee4d0755c5784c3dd647528b3c7bc (diff) | |
| download | coreboot-aef0d6b0a7ec867ee29acf9e1c695be27626f239.tar.xz | |
mb/google/reef/sand: Override USB2 phy settings
Sometimes the USB device is not detected. USB2 port#1 and #4 PHY register need
to be overridden.
port#1:
PERPORTPETXISET = 4
PERPORTTXISET = 4
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0
port#4:
PERPORTPETXISET = 7
PERPORTTXISET = 7
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0
BUG=b:72623892
BRANCH=master
TEST=emerge-sand coreboot chromeos-bootimage
Change-Id: I4051aefbec4583bb1f8babec08fdbeb27f749769
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/23879
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/reef')
| -rw-r--r-- | src/mainboard/google/reef/variants/sand/devicetree.cb | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index 0735a35e10..a6692e6bf7 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -112,6 +112,22 @@ chip soc/intel/apollolake # Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000" + # Override USB2 PER PORT register (PORT 1) + register "usb2eye[1]" = "{ + .Usb20PerPortPeTxiSet = 4, + .Usb20PerPortTxiSet = 4, + .Usb20IUsbTxEmphasisEn = 1, + .Usb20PerPortTxPeHalf = 0, + }" + + # Override USB2 PER PORT register (PORT 4) + register "usb2eye[4]" = "{ + .Usb20PerPortPeTxiSet = 7, + .Usb20PerPortTxiSet = 7, + .Usb20IUsbTxEmphasisEn = 1, + .Usb20PerPortTxPeHalf = 0, + }" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF |