summaryrefslogtreecommitdiff
path: root/src/mainboard/google/reef
diff options
context:
space:
mode:
authorNico Huber <nico.h@gmx.de>2016-12-07 19:29:08 +0100
committerNico Huber <nico.h@gmx.de>2017-03-10 17:39:46 +0100
commite392f414cd27edba78f02a5e9274126aa0a80f89 (patch)
tree1e8d6ae67bbc6a84ff4b7396a51f91e22c0730a6 /src/mainboard/google/reef
parent589fc3473ed463283d9be168a67c2de1f3612c0a (diff)
downloadcoreboot-e392f414cd27edba78f02a5e9274126aa0a80f89.tar.xz
soc/intel/broadwell: Rework IGD's CDClk selection
CDClk selection was wrong in some corner cases (e.g. ULX SKUs) and, for Broadwell, never took the devicetree config into account. Rewrite the selection with the following in mind: o cpu_is_ult() might return `true` for ULX SKUs, too, o ULX and Broadwell-ULT SKUs can be `overclocked` with additional cooling, so leave that as devicetree option. For Haswell, the following frequency selections are valid: o ULX: 337.5MHz by default, 450MHz optional o ULT: 450MHz only (maybe 337.5MHz too, documentation varies, it wasn't selectable before either) o others: 540MHz by default, 450MHz optional For Broadwell: o ULX: 450MHz by default, 337.5MHz / 540MHz optional o ULT: 540MHz by default, 337.5MHz / 450MHz / 675MHz optional o others: 667MHz by default, 337.5MHz / 450MHz / 540MHz optional Side effects: A too high setting in the devicetree results in the highest possible frequency now, Haswell non-ULT/ULX defaults to 540MHz instead of 450MHz. Change-Id: Iec12752f2a47bf4a5ae6077c75790eae9378c1b2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17768 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google/reef')
0 files changed, 0 insertions, 0 deletions