diff options
| author | Furquan Shaikh <furquan@google.com> | 2016-06-14 17:28:51 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-06-16 08:14:39 +0200 |
| commit | 2c4a60da35f5f3334e5a35c3330712f2241ecf58 (patch) | |
| tree | b30f1b32a5c7574852dee6ae3b074156efdb9536 /src/mainboard/google/reef | |
| parent | 5a3833d2d33a8b89b814cfd10e7f84b0f510320a (diff) | |
| download | coreboot-2c4a60da35f5f3334e5a35c3330712f2241ecf58.tar.xz | |
google/reef: Update flash size to 16MiB
Use entire 16MiB flash size on reef. Adjust SIGN_CSE region
accordingly.
BUG=chrome-os-partner:54390
Change-Id: I94de509bdb2aa94625814123bf4d9758bfa37fc9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15191
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/google/reef')
| -rw-r--r-- | src/mainboard/google/reef/Kconfig | 5 | ||||
| -rw-r--r-- | src/mainboard/google/reef/chromeos.fmd | 16 |
2 files changed, 10 insertions, 11 deletions
diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index c1ccc5c819..fd948c7cd7 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -3,8 +3,7 @@ if BOARD_GOOGLE_REEF config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_INTEL_APOLLOLAKE - # FIXME(adurbin): this SPI part is really 16MiB - select BOARD_ROMSIZE_KB_8192 + select BOARD_ROMSIZE_KB_16384 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME @@ -19,7 +18,7 @@ config BOOT_MEDIA_SPI_BUS config IFD_BIOS_END hex - default 0x77F000 + default 0xF7F000 config IFD_BIOS_START hex diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index be87cb46ad..49f3497d93 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -1,8 +1,8 @@ -FLASH 8M { - WP_RO@0x0 0x400000 { +FLASH 16M { + WP_RO@0x0 0x800000 { SI_DESC@0x0 0x1000 IFWI@0x1000 0x1ff000 - RO_SECTION@0x200000 0x200000 { + RO_SECTION@0x200000 0x600000 { RO_VPD@0x0 0x4000 FMAP@0x4000 0x800 RO_FRID@0x4800 0x40 @@ -10,10 +10,10 @@ FLASH 8M { COREBOOT(CBFS)@0x5000 0x17b000 GBB@0x180000 0x40000 # logical boot partition 2. Remove with updated CSE - SIGN_CSE@0x1c0000 0x10000 + SIGN_CSE@0x5c0000 0x10000 } } - MISC_RW@0x400000 0x1a000 { + MISC_RW@0x800000 0x1a000 { RW_MRC_CACHE@0x0 0x10000 RW_ELOG@0x10000 0x4000 RW_SHARED@0x14000 0x4000 { @@ -22,16 +22,16 @@ FLASH 8M { } RW_VPD@0x18000 0x2000 } - RW_SECTION_A@0x41a000 0x173000 { + RW_SECTION_A@0x81a000 0x173000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x162fc0 RW_FWID_A@0x172fc0 0x40 } - RW_SECTION_B@0x58d000 0x173000 { + RW_SECTION_B@0x98d000 0x173000 { VBLOCK_B@0x0 0x10000 FW_MAIN_B(CBFS)@0x10000 0x162fc0 RW_FWID_B@0x172fc0 0x40 } - DEVICE_EXTENSION@0x77f000 0x80000 + DEVICE_EXTENSION@0xf7f000 0x80000 } |