diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-08-03 17:15:02 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-08-06 04:36:13 +0200 |
| commit | dfb373541b71e4a8a41d1b4b5407c47ca0d9b5bd (patch) | |
| tree | 727f042df32fa45a1d9dfba80bf80820dcd66465 /src/mainboard/google/reef | |
| parent | 37319036463561521a0ffd613e4c387e65d2ace0 (diff) | |
| download | coreboot-dfb373541b71e4a8a41d1b4b5407c47ca0d9b5bd.tar.xz | |
google/reef: Enable I2C2 for use in bootblock
Enable I2C bus 2 for early init so it can be used by vboot for TPM
communication for verifying the memory init code.
BUG=chrome-os-partner:53336
BRANCH=none
TEST=build and boot on reef
Change-Id: Id4940ab01d8ccf288ab0a7a9a2f19867ed464e8d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16059
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/reef')
| -rw-r--r-- | src/mainboard/google/reef/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/google/reef/gpio.h | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index 5e68d3720c..ea3b20f2e2 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -43,6 +43,9 @@ chip soc/intel/apollolake register "gpe0_dw2" = "PMC_GPE_N_63_32" register "gpe0_dw3" = "PMC_GPE_SW_31_0" + # Enable I2C2 bus early for TPM access + register "i2c[2].early_init" = "1" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 5eb1d1dc29..4230c62ef7 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -344,6 +344,9 @@ static const struct pad_config gpio_table[] = { /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ + /* I2C2 - TPM */ + PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ + PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ }; /* |