google/rikku: Upstream Acer Chromebox CXI2

Migrate google/rikku (Acer Chromebox CXI2) from Chromium tree to
upstream, using google/guado as a baseline.

original source:
branch firmware-rikku-6301.110.B
commit 2e71207 [CHERRY-PICK: broadwell: Update to microcode 0x1F]

TEST=built and booted Linux on rikku with full functionality

blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.bin)
external reference code (refcode.elf)

Change-Id: Iba618a0b2cf2d613f6429b3e7606e0b47fa97a4d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12802
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 95 insertions, 0 deletions

diff --git a/src/mainboard/google/rikku/chromeos.c b/src/mainboard/google/rikku/chromeos.c
new file mode 100644
index 0000000000..d440968c41
--- /dev/null
+++ b/src/mainboard/google/rikku/chromeos.c
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <console/console.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/gpio.h>
+#include <soc/sata.h>
+
+#define GPIO_SPI_WP	58
+#define GPIO_REC_MODE	12
+
+#define FLAG_SPI_WP	0
+#define FLAG_REC_MODE	1
+#define FLAG_DEV_MODE	2
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {
+		{GPIO_SPI_WP, ACTIVE_HIGH, 0, "write protect"},
+		{GPIO_REC_MODE, ACTIVE_LOW,
+			get_recovery_mode_switch(), "recovery"},
+		{-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
+		{-1, ACTIVE_HIGH, 1, "lid"},
+		{-1, ACTIVE_HIGH, 0, "power"},
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+#endif
+
+int get_write_protect_state(void)
+{
+	device_t dev;
+#ifdef __PRE_RAM__
+	dev = PCI_DEV(0, 0x1f, 2);
+#else
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
+#endif
+	return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
+}
+
+int get_developer_mode_switch(void)
+{
+	return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+	device_t dev;
+#ifdef __PRE_RAM__
+	dev = PCI_DEV(0, 0x1f, 2);
+#else
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
+#endif
+	return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
+}
+
+#ifdef __PRE_RAM__
+void save_chromeos_gpios(void)
+{
+	u32 flags = 0;
+
+	/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
+	if (get_gpio(GPIO_SPI_WP))
+		flags |= (1 << FLAG_SPI_WP);
+
+	/* Recovery: GPIO12 = RECOVERY_L, active low */
+	if (!get_gpio(GPIO_REC_MODE))
+		flags |= (1 << FLAG_REC_MODE);
+
+	/* Developer: Virtual */
+
+	pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
+}
+#endif