google/rikku: Upstream Acer Chromebox CXI2

Migrate google/rikku (Acer Chromebox CXI2) from Chromium tree to
upstream, using google/guado as a baseline.

original source:
branch firmware-rikku-6301.110.B
commit 2e71207 [CHERRY-PICK: broadwell: Update to microcode 0x1F]

TEST=built and booted Linux on rikku with full functionality

blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.bin)
external reference code (refcode.elf)

Change-Id: Iba618a0b2cf2d613f6429b3e7606e0b47fa97a4d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12802
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 63 insertions, 0 deletions

diff --git a/src/mainboard/google/rikku/romstage.c b/src/mainboard/google/rikku/romstage.c
new file mode 100644
index 0000000000..5f06ed9f12
--- /dev/null
+++ b/src/mainboard/google/rikku/romstage.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <string.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/romstage.h>
+#include <mainboard/google/rikku/spd/spd.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8772f/it8772f.h>
+#include "gpio.h"
+#include "onboard.h"
+
+void mainboard_romstage_entry(struct romstage_params *rp)
+{
+	struct pei_data pei_data;
+
+	post_code(0x32);
+
+	/* Initialize GPIOs */
+	init_gpios(mainboard_gpio_config);
+
+	/* Fill out PEI DATA */
+	memset(&pei_data, 0, sizeof(pei_data));
+	mainboard_fill_pei_data(&pei_data);
+	mainboard_fill_spd_data(&pei_data);
+	rp->pei_data = &pei_data;
+
+	/* Call into the real romstage main with this board's attributes. */
+	romstage_common(rp);
+}
+
+void mainboard_pre_console_init(void)
+{
+	/* Early SuperIO setup */
+	ite_kill_watchdog(IT8772F_GPIO_DEV);
+	it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV);
+	ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+	/* Turn On GPIO10.LED */
+	it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */,
+		0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */,
+		0x01 /* output */, 0x01 /* 1=Simple IO function */,
+		SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
+
+}