summaryrefslogtreecommitdiff
path: root/src/mainboard/google/rush
diff options
context:
space:
mode:
authorTom Warren <twarren@nvidia.com>2014-07-30 16:26:21 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-03-25 22:31:23 +0100
commit472e0393eb1a8f212994f7152daa4eb5e8554ef3 (patch)
tree601f648e6795a189b4ce5f4f432bf6f9017fe832 /src/mainboard/google/rush
parent61abe1d32bd90654292fd98e6b0fec4581144bf2 (diff)
downloadcoreboot-472e0393eb1a8f212994f7152daa4eb5e8554ef3.tar.xz
ryu: Add mainboard_init_xxx functions to get it building again
Rush has its EC on SPI, and Ryu has it on I2C, so need both mainboard_init_ec_spi and mainboard_init_ec_i2c in both builds, due to romstage.c being in the common tegra132 subdir. BUG=none BRANCH=rush_ryu TEST=Built both rush and rush_ryu images OK. Will try to boot on Ryu later. Change-Id: Iddbf9e9f6de7ba7244f9dd2e810fb6178937c85a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d8b81717c366d19b43964bed3c4047598db4495 Original-Change-Id: I48d9530697d5669177ecd9ba3c34360197002003 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210595 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8900 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/rush')
-rw-r--r--src/mainboard/google/rush/romstage.c29
1 files changed, 29 insertions, 0 deletions
diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c
index 7c01a30604..8edcba8d6a 100644
--- a/src/mainboard/google/rush/romstage.c
+++ b/src/mainboard/google/rush/romstage.c
@@ -51,6 +51,35 @@ void mainboard_init_tpm_i2c(void)
configure_tpm_i2c_bus();
}
+void mainboard_init_ec_spi(void)
+{
+ clock_enable_clear_reset(0, CLK_H_SBC1, 0, 0, 0, 0);
+
+ // SPI1 MOSI
+ pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
+ PINMUX_PULL_NONE |
+ PINMUX_INPUT_ENABLE);
+ // SPI1 MISO
+ pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
+ PINMUX_PULL_NONE |
+ PINMUX_INPUT_ENABLE);
+ // SPI1 SCLK
+ pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
+ PINMUX_PULL_NONE |
+ PINMUX_INPUT_ENABLE);
+ // SPI1 CS0
+ pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
+ PINMUX_PULL_NONE |
+ PINMUX_INPUT_ENABLE);
+
+ clock_configure_source(sbc1, CLK_M, 500);
+}
+
+void mainboard_init_ec_i2c(void)
+{
+ /* Empty - Rush uses SPI to communicate with the EC */
+}
+
void mainboard_configure_pmc(void)
{
}