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authorJimmy Zhang <jimmzhang@nvidia.com>2015-01-06 12:06:51 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-14 09:04:24 +0200
commitcfc0cff14b51f06980362ecb15466c7f539c99d2 (patch)
tree53721215a04f2d89345f165f24dd3a8a7c1a14b1 /src/mainboard/google/rush
parentfb391fa24c33b29ac0fde386133ca168a527eefe (diff)
downloadcoreboot-cfc0cff14b51f06980362ecb15466c7f539c99d2.tar.xz
rush: devicetree: Define default dp panel parameters
DP panel parameters generally can be retrieved thru edid. The parameters specified here will be used when edid fetching failed. BUG=chrome-os-partner:34336 BRANCH=none TEST=build rush and ryu Change-Id: I39e25c873561f75394408f6635aaa2e88b67d846 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c02facb9753de08f66f3ae40d7dca1eba50febc5 Original-Change-Id: I4785eca3ec03b48e8780ebf02389e9b46317e96d Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/238941 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9612 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/rush')
-rw-r--r--src/mainboard/google/rush/devicetree.cb68
1 files changed, 67 insertions, 1 deletions
diff --git a/src/mainboard/google/rush/devicetree.cb b/src/mainboard/google/rush/devicetree.cb
index 98284fc4e6..b01ca366ac 100644
--- a/src/mainboard/google/rush/devicetree.cb
+++ b/src/mainboard/google/rush/devicetree.cb
@@ -1,7 +1,7 @@
##
## This file is part of the coreboot project.
##
-## Copyright 2014 Google Inc.
+## Copyright 2015 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -24,4 +24,70 @@ chip soc/nvidia/tegra132
device cpu 0 on end
device cpu 1 on end
end
+
+ register "display_controller" = "TEGRA_ARM_DISPLAYA"
+ register "xres" = "1366"
+ register "yres" = "768"
+
+ # framebuffer resolution
+ register "display_xres" = "1368"
+ register "display_yres" = "678"
+
+ # bits per pixel and color depth
+ register "framebuffer_bits_per_pixel" = "16"
+ register "color_depth" = "6"
+
+ register "panel_bits_per_pixel" = "18"
+
+# How to compute these: xrandr --verbose will give you this:
+#Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm
+# 2560 2608 2640 2720 hborder 0
+# 1700 1703 1713 1749 vborder 0
+#Then you can compute your values:
+#H front porch = 2608 - 2560 = 48
+#H sync = 2640 - 2608 = 32
+#H back porch = 2720 - 2640 = 80
+#V front porch = 1703 - 1700 = 3
+#V sync = 1713 - 1703 = 10
+#V back porch = 1749 - 1713 = 36
+#href_to_sync and vref_to_sync are from the vendor
+#this is just an example for a Pixel panel; other panels differ.
+# Here is a peppy panel:
+# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred
+# h: width 1366 start 1502 end 1532 total 1592
+# v: height 768 start 776 end 788 total 800
+ register "href_to_sync" = "1"
+ register "hfront_porch" = "136"
+ register "hsync_width" = "30"
+ register "hback_porch" = "60"
+
+ register "vref_to_sync" = "1"
+ register "vfront_porch" = "8"
+ register "vsync_width" = "12"
+ register "vback_porch" = "12"
+
+ register "pixel_clock" = "76400000"
+
+ register "win_opt" = "SOR_ENABLE"
+
+ #
+ # dp specific fields
+ #
+ register "dp.pwm" = "1"
+
+ # various panel delay time
+ register "dp.vdd_to_hpd_delay_ms" = "200"
+ register "dp.hpd_unplug_min_us" = "2000"
+ register "dp.hpd_plug_min_us" = "250"
+ register "dp.hpd_irq_min_us" = "250"
+
+ # link configurations
+ register "dp.lane_count" = "1"
+ register "dp.enhanced_framing" = "1"
+ register "dp.link_bw" = "10"
+ # "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h
+
+ register "dp.drive_current" = "0x40404040"
+ register "dp.preemphasis" = "0x0f0f0f0f"
+ register "dp.postcursor" = "0"
end