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authorFurquan Shaikh <furquan@google.com>2014-10-04 17:05:50 -0700
committerAaron Durbin <adurbin@google.com>2015-04-08 20:16:41 +0200
commit74d3b3a732e2f370827e50984d45f031b0dfcffb (patch)
treeb41c854e16813265c39486fe280d1f643f0cf4b2 /src/mainboard/google/rush
parentb4006438855ec8d5e1c0e5012d7b0b85b5416dbb (diff)
downloadcoreboot-74d3b3a732e2f370827e50984d45f031b0dfcffb.tar.xz
rush: Add vboot2 support
CQ-DEPEND=CL:221601, CL:*178568 BUG=chrome-os-partner:32684 BRANCH=None TEST=Compiles successfully Original-Change-Id: I50d0475dbe1390b640a726c259364f36abcbebe0 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221579 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 14e348721399f13a52258faa16769b0ebb5b511f) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I2683cb29c7a93f3f4aba0d7b9a56a1ca209518a0 Reviewed-on: http://review.coreboot.org/9432 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/rush')
-rw-r--r--src/mainboard/google/rush/Kconfig5
-rw-r--r--src/mainboard/google/rush/Makefile.inc5
-rw-r--r--src/mainboard/google/rush/memlayout.ld4
-rw-r--r--src/mainboard/google/rush/verstage.c51
4 files changed, 64 insertions, 1 deletions
diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig
index 94cbed1ea7..95597b00f9 100644
--- a/src/mainboard/google/rush/Kconfig
+++ b/src/mainboard/google/rush/Kconfig
@@ -78,9 +78,12 @@ config BOOT_MEDIA_SPI_CHIP_SELECT
help
Which chip select to use for boot media.
+# For rush, we are using vboot2. Thus, index for stages:
+# VBOOT_ROMSTAGE_INDEX -> Use default value of 0x2
+# VBOOT_RAMSTAGE_INDEX -> Use 0x3
config VBOOT_RAMSTAGE_INDEX
hex
- default 0x2
+ default 0x3
config DRIVER_TPM_I2C_BUS
hex
diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc
index e41745f1a1..a4d0135f41 100644
--- a/src/mainboard/google/rush/Makefile.inc
+++ b/src/mainboard/google/rush/Makefile.inc
@@ -31,6 +31,10 @@ bootblock-y += bootblock.c
bootblock-y += pmic.c
bootblock-y += reset.c
+verstage-y += verstage.c
+verstage-y += chromeos.c
+verstage-y += reset.c
+
romstage-y += romstage.c
romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
@@ -44,3 +48,4 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld
+verstage-y += memlayout.ld
diff --git a/src/mainboard/google/rush/memlayout.ld b/src/mainboard/google/rush/memlayout.ld
index 85f4a97855..5bd72e5126 100644
--- a/src/mainboard/google/rush/memlayout.ld
+++ b/src/mainboard/google/rush/memlayout.ld
@@ -1 +1,5 @@
+#if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)
+#include <soc/memlayout_vboot2.ld>
+#else
#include <soc/memlayout_vboot.ld>
+#endif
diff --git a/src/mainboard/google/rush/verstage.c b/src/mainboard/google/rush/verstage.c
new file mode 100644
index 0000000000..0150e465a7
--- /dev/null
+++ b/src/mainboard/google/rush/verstage.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <soc/addressmap.h>
+#include <soc/funitcfg.h>
+#include <soc/padconfig.h>
+#include <soc/verstage.h>
+#include <soc/nvidia/tegra/i2c.h>
+
+static const struct pad_config i2cpad[] = {
+ /* TPM I2C */
+ PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
+ PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
+};
+
+static const struct pad_config spipad[] = {
+ /* EC on SPI1: mosi, miso, clk, cs */
+ PAD_CFG_SFIO(ULPI_CLK, PINMUX_INPUT_ENABLE, SPI1),
+ PAD_CFG_SFIO(ULPI_DIR, PINMUX_INPUT_ENABLE, SPI1),
+ PAD_CFG_SFIO(ULPI_NXT, PINMUX_INPUT_ENABLE, SPI1),
+ PAD_CFG_SFIO(ULPI_STP, PINMUX_INPUT_ENABLE, SPI1),
+};
+
+static const struct funit_cfg funitcfgs[] = {
+ FUNIT_CFG(SBC1, CLK_M, 3000, spipad, ARRAY_SIZE(spipad)),
+ FUNIT_CFG(I2C3, PLLP, 400, i2cpad, ARRAY_SIZE(i2cpad)),
+};
+
+void verstage_mainboard_init(void)
+{
+ soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
+
+ /* TPM I2C bus */
+ i2c_init(2);
+}