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authorFurquan Shaikh <furquan@google.com>2014-08-05 21:14:54 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-03-26 00:27:19 +0100
commitedb58fd2aa2d0f12c459bc94dc5b3d497e648eaa (patch)
tree6a8cdc5ba7739a4da54e484b499bbe48ec74faa1 /src/mainboard/google/rush
parenta69a67be13425b769efd9ff2a882de77365be00e (diff)
downloadcoreboot-edb58fd2aa2d0f12c459bc94dc5b3d497e648eaa.tar.xz
rush: Add usb support for rush in coreboot
BUG=chrome-os-partner:31293 BRANCH=None TEST=With non-cacheable memory region and dma range addition, booting from usb reaches the same point as mmc. Change-Id: I218c751f41fb881af4fed0bcccc378dde1fd07b4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a26e07b58f454c598bf5b7a4940c238135548bbd Original-Change-Id: I1083f8de2bfbe9a233d317b29b8fc56f47c7061d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211039 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8937 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/rush')
-rw-r--r--src/mainboard/google/rush/mainboard.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c
index 35417f07ce..a143972f2c 100644
--- a/src/mainboard/google/rush/mainboard.c
+++ b/src/mainboard/google/rush/mainboard.c
@@ -28,6 +28,7 @@
#include <soc/addressmap.h>
#include <soc/padconfig.h>
#include <soc/funitcfg.h>
+#include <soc/nvidia/tegra/usb.h>
static const struct pad_config sdmmc3_pad[] = {
/* MMC3(SDCARD) */
@@ -60,6 +61,13 @@ static const struct pad_config sdmmc4_pad[] = {
PAD_CFG_SFIO(SDMMC4_DAT7, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
};
+static const struct pad_config padcfgs[] = {
+ /* We pull the USB VBUS signals up but keep them as inputs since the
+ * voltage source likes to drive them low on overcurrent conditions */
+ PAD_CFG_GPIO_INPUT(USB_VBUS_EN0, PINMUX_PULL_UP),
+ PAD_CFG_GPIO_INPUT(USB_VBUS_EN1, PINMUX_PULL_UP),
+};
+
static const struct funit_cfg funitcfgs[] = {
FUNIT_CFG(SDMMC3, PLLP, 48000, sdmmc3_pad, ARRAY_SIZE(sdmmc3_pad)),
FUNIT_CFG(SDMMC4, PLLP, 48000, sdmmc4_pad, ARRAY_SIZE(sdmmc4_pad)),
@@ -72,11 +80,21 @@ static void setup_ec_spi(void)
spi = tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
}
+static void setup_usb(void)
+{
+ clock_enable_clear_reset(CLK_L_USBD, CLK_H_USB3, 0, 0, 0, 0);
+
+ usb_setup_utmip((void *)TEGRA_USBD_BASE);
+ usb_setup_utmip((void *)TEGRA_USB3_BASE);
+}
+
static void mainboard_init(device_t dev)
{
+ soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
setup_ec_spi();
+ setup_usb();
}
static void mainboard_enable(device_t dev)