diff options
| author | Jimmy Zhang <jimmzhang@nvidia.com> | 2014-10-31 18:26:11 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-10 12:01:01 +0200 |
| commit | ae272297aaeb3e383eb1cd67f104e563a06d957a (patch) | |
| tree | b6f3fbce12ef039c73092f194eb8cdc997aac907 /src/mainboard/google/rush_ryu/pmic.c | |
| parent | 58901b6b660783a47c308c1e66acfa84ee62d7e5 (diff) | |
| download | coreboot-ae272297aaeb3e383eb1cd67f104e563a06d957a.tar.xz | |
ryu: Enhance pmic access functions
1. Add page address, an i2c address, into register address table
2. Add pmic read function
3. Add more registers and setting values.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: Ieef0737205b20add3ff8990f62dd8585a4e8c557
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6dcf42c299e25023991be331b724acd0fd9f32c2
Original-Change-Id: I227b3e9390e6fc020707d4730c19945760df6ca2
Original-Reviewed-on: https://chromium-review.googlesource.com/226902
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: http://review.coreboot.org/9420
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/rush_ryu/pmic.c')
| -rw-r--r-- | src/mainboard/google/rush_ryu/pmic.c | 34 |
1 files changed, 20 insertions, 14 deletions
diff --git a/src/mainboard/google/rush_ryu/pmic.c b/src/mainboard/google/rush_ryu/pmic.c index a816e8ac14..00d1ab476f 100644 --- a/src/mainboard/google/rush_ryu/pmic.c +++ b/src/mainboard/google/rush_ryu/pmic.c @@ -27,30 +27,38 @@ #include "pmic.h" #include "reset.h" -/* A44/Ryu has a TI 65913 PMIC on bus 4 (PWR_I2C) */ - -enum { - TI65913_I2C_ADDR = 0x58 -}; +#define PAGE_ADDR(reg) ((reg >> 8) & 0xff) +#define PAGE_OFFSET(reg) (reg & 0xff) struct ti65913_init_reg { - u8 reg; + u16 reg; u8 val; u8 delay; }; static struct ti65913_init_reg init_list[] = { //TODO(twarren@nvidia.com): Add slams back to defaults -// {TI65913_SMPS12_CTRL, 0x01, 0}, // {TI65913_SMPS12_VOLTAGE, 0x38, 0}, +// {TI65913_SMPS12_CTRL, 0x01, 1}, //etc. }; -void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay) +int pmic_read_reg(unsigned bus, uint16_t reg, uint8_t *data) { - if (i2c_writeb(bus, TI65913_I2C_ADDR, reg, val)) { - printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", - __func__, reg, val); + if (i2c_readb(bus, PAGE_ADDR(reg), PAGE_OFFSET(reg), data)) { + printk(BIOS_ERR, "%s: page = 0x%02X, reg = 0x%02X failed!\n", + __func__, PAGE_ADDR(reg), PAGE_OFFSET(reg)); + return -1; + } + return 0; +} + +void pmic_write_reg(unsigned bus, uint16_t reg, uint8_t val, int delay) +{ + if (i2c_writeb(bus, PAGE_ADDR(reg), PAGE_OFFSET(reg), val)) { + printk(BIOS_ERR, "%s: page = 0x%02X, reg = 0x%02X, " + "value = 0x%02X failed!\n", + __func__, PAGE_ADDR(reg), PAGE_OFFSET(reg), val); /* Reset the SoC on any PMIC write error */ cpu_reset(); } else { @@ -71,14 +79,12 @@ static void pmic_slam_defaults(unsigned bus) void pmic_init(unsigned bus) { - /* Don't need to set up VDD_CORE - already done - by EC ?? */ - /* Restore PMIC POR defaults, in case kernel changed 'em */ pmic_slam_defaults(bus); /* A44: Set VDD_CPU to 1.0V. */ - pmic_write_reg(bus, TI65913_SMPS12_CTRL, 0x01, 1); pmic_write_reg(bus, TI65913_SMPS12_VOLTAGE, 0x38, 0); + pmic_write_reg(bus, TI65913_SMPS12_CTRL, 0x01, 1); printk(BIOS_DEBUG, "PMIC init done\n"); } |