diff options
author | Tom Warren <twarren@nvidia.com> | 2014-07-16 11:09:39 -0700 |
---|---|---|
committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-13 00:10:33 +0100 |
commit | a6ca9353a878ffd874b4cec44e60b01cc6ab508c (patch) | |
tree | a493f634cb6e2cb1098b444af2687afcf755119c /src/mainboard/google/rush_ryu/pmic.c | |
parent | 2525885576e883f1018c9fb34fde0cce4fcd046a (diff) | |
download | coreboot-a6ca9353a878ffd874b4cec44e60b01cc6ab508c.tar.xz |
ryu: Add TPS65913 regs/init for VDD_CPU 1.0V
Other default slams should be added later to the init table
once we know what the kernel touches. But for now, only VDD_CPU
is needed.
Also slipped in a minor name change in mainboard.c
BRANCH=none
BUG=none
TEST=none, no HW here for me to test on yet
Change-Id: Ifbe86192449ed0466085808a0a12a15a7b6a1795
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/208385
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 53b332fb12cd685fbec265695333a70c4064524c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8645
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/rush_ryu/pmic.c')
-rw-r--r-- | src/mainboard/google/rush_ryu/pmic.c | 61 |
1 files changed, 16 insertions, 45 deletions
diff --git a/src/mainboard/google/rush_ryu/pmic.c b/src/mainboard/google/rush_ryu/pmic.c index 5fc3b176f4..8d5ea7aeec 100644 --- a/src/mainboard/google/rush_ryu/pmic.c +++ b/src/mainboard/google/rush_ryu/pmic.c @@ -23,45 +23,31 @@ #include <device/i2c.h> #include <stdint.h> #include <stdlib.h> - -#include "boardid.h" #include "pmic.h" #include "reset.h" +/* A44/Ryu has a TI 65913 PMIC on bus 4 (PWR_I2C) */ + enum { - AS3722_I2C_ADDR = 0x40 + TI65913_I2C_ADDR = 0x58 }; -struct as3722_init_reg { +struct ti65913_init_reg { u8 reg; u8 val; u8 delay; }; -static struct as3722_init_reg init_list[] = { - {AS3722_SDO0, 0x3C, 1}, - {AS3722_SDO1, 0x32, 0}, - {AS3722_LDO3, 0x59, 0}, - {AS3722_SDO2, 0x3C, 0}, - {AS3722_SDO3, 0x00, 0}, - {AS3722_SDO4, 0x00, 0}, - {AS3722_SDO5, 0x50, 0}, - {AS3722_SDO6, 0x28, 1}, - {AS3722_LDO0, 0x8A, 0}, - {AS3722_LDO1, 0x00, 0}, - {AS3722_LDO2, 0x10, 0}, - {AS3722_LDO4, 0x00, 0}, - {AS3722_LDO5, 0x00, 0}, - {AS3722_LDO6, 0x00, 0}, - {AS3722_LDO7, 0x00, 0}, - {AS3722_LDO9, 0x00, 0}, - {AS3722_LDO10, 0x00, 0}, - {AS3722_LDO11, 0x00, 1}, +static struct ti65913_init_reg init_list[] = { +//TODO(twarren@nvidia.com): Add slams back to defaults +// {TI65913_SMPS12_CTRL, 0x01, 0}, +// {TI65913_SMPS12_VOLTAGE, 0x38, 0}, +//etc. }; static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay) { - if (i2c_writeb(bus, AS3722_I2C_ADDR, reg, val)) { + if (i2c_writeb(bus, TI65913_I2C_ADDR, reg, val)) { printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", __func__, reg, val); /* Reset the SoC on any PMIC write error */ @@ -75,38 +61,23 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay) static void pmic_slam_defaults(unsigned bus) { int i; + for (i = 0; i < ARRAY_SIZE(init_list); i++) { - struct as3722_init_reg *reg = &init_list[i]; + struct ti65913_init_reg *reg = &init_list[i]; pmic_write_reg(bus, reg->reg, reg->val, reg->delay); } } void pmic_init(unsigned bus) { - /* - * Don't need to set up VDD_CORE - already done - by OTP - * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. - * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. - */ + /* Don't need to set up VDD_CORE - already done - by EC ?? */ /* Restore PMIC POR defaults, in case kernel changed 'em */ pmic_slam_defaults(bus); - /* SDO0: Set VDD_CPU to 1.2V. */ - pmic_write_reg(bus, 0x00, 0x50, 1); - - /* SDO6: Set VDD_GPU to 1.0V. */ - pmic_write_reg(bus, 0x06, 0x28, 1); - - /* LDO2: Set +1.2V_GEN_AVDD to 1.2V */ - pmic_write_reg(bus, 0x12, 0x10, 1); - - /* - * Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set - * the value (register 0x20 bit 4) - */ - pmic_write_reg(bus, 0x0c, 0x07, 0); - pmic_write_reg(bus, 0x20, 0x10, 1); + /* A44: Set VDD_CPU to 1.0V. */ + pmic_write_reg(bus, TI65913_SMPS12_CTRL, 0x01, 1); + pmic_write_reg(bus, TI65913_SMPS12_VOLTAGE, 0x38, 0); printk(BIOS_DEBUG, "PMIC init done\n"); } |