diff options
author | Tom Warren <twarren@nvidia.com> | 2014-07-16 11:09:39 -0700 |
---|---|---|
committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-13 00:10:33 +0100 |
commit | a6ca9353a878ffd874b4cec44e60b01cc6ab508c (patch) | |
tree | a493f634cb6e2cb1098b444af2687afcf755119c /src/mainboard/google/rush_ryu/pmic.h | |
parent | 2525885576e883f1018c9fb34fde0cce4fcd046a (diff) | |
download | coreboot-a6ca9353a878ffd874b4cec44e60b01cc6ab508c.tar.xz |
ryu: Add TPS65913 regs/init for VDD_CPU 1.0V
Other default slams should be added later to the init table
once we know what the kernel touches. But for now, only VDD_CPU
is needed.
Also slipped in a minor name change in mainboard.c
BRANCH=none
BUG=none
TEST=none, no HW here for me to test on yet
Change-Id: Ifbe86192449ed0466085808a0a12a15a7b6a1795
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/208385
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 53b332fb12cd685fbec265695333a70c4064524c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8645
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/rush_ryu/pmic.h')
-rw-r--r-- | src/mainboard/google/rush_ryu/pmic.h | 89 |
1 files changed, 66 insertions, 23 deletions
diff --git a/src/mainboard/google/rush_ryu/pmic.h b/src/mainboard/google/rush_ryu/pmic.h index b56c513416..1f102a70c2 100644 --- a/src/mainboard/google/rush_ryu/pmic.h +++ b/src/mainboard/google/rush_ryu/pmic.h @@ -17,32 +17,75 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __MAINBOARD_GOOGLE_RUSH_PMIC_H__ -#define __MAINBOARD_GOOGLE_RUSH_PMIC_H__ +#ifndef __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__ +#define __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__ +/* A44/Ryu has a TI 65913 PMIC */ enum { - AS3722_SDO0 = 0, - AS3722_SDO1, - AS3722_SDO2, - AS3722_SDO3, - AS3722_SDO4, - AS3722_SDO5, - AS3722_SDO6, - - AS3722_LDO0 = 0x10, - AS3722_LDO1, - AS3722_LDO2, - AS3722_LDO3, - AS3722_LDO4, - AS3722_LDO5, - AS3722_LDO6, - AS3722_LDO7, - - AS3722_LDO9 = 0x19, - AS3722_LDO10, - AS3722_LDO11, + TI65913_SMPS12_CTRL = 0x20, + TI65913_SMPS12_TSTEP, + TI65913_SMPS12_FORCE, + TI65913_SMPS12_VOLTAGE, + + TI65913_SMPS3_CTRL, + TI65913_SMPS3_VOLTAGE = 0x27, + + TI65913_SMPS45_CTRL = 0x28, + TI65913_SMPS45_TSTEP, + TI65913_SMPS45_FORCE, + TI65913_SMPS45_VOLTAGE, + + TI65913_SMPS6_CTRL = 0x2C, + TI65913_SMPS6_TSTEP, + TI65913_SMPS6_FORCE, + TI65913_SMPS6_VOLTAGE, + + TI65913_SMPS7_CTRL = 0x30, + TI65913_SMPS7_VOLTAGE = 0x33, + + TI65913_SMPS8_CTRL = 0x34, + TI65913_SMPS8_TSTEP, + TI65913_SMPS8_FORCE, + TI65913_SMPS8_VOLTAGE, + + TI65913_SMPS9_CTRL = 0x38, + TI65913_SMPS9_VOLTAGE = 0x3B, + + TI65913_SMPS10_CTRL = 0x3C, + TI65913_SMPS10_STATUS = 0x3F, + + TI65913_LDO1_CTRL = 0x50, + TI65913_LDO1_VOLTAGE, + TI65913_LDO2_CTRL, + TI65913_LDO2_VOLTAGE, + TI65913_LDO3_CTRL, + TI65913_LDO3_VOLTAGE, + TI65913_LDO4_CTRL, + TI65913_LDO4_VOLTAGE, + TI65913_LDO5_CTRL, + TI65913_LDO5_VOLTAGE, + TI65913_LDO6_CTRL, + TI65913_LDO6_VOLTAGE, + TI65913_LDO7_CTRL, + TI65913_LDO7_VOLTAGE, + TI65913_LDO8_CTRL, + TI65913_LDO8_VOLTAGE, + TI65913_LDO9_CTRL, + TI65913_LDO9_VOLTAGE, + + TI65913_LDOLN_CTRL = 0x62, + TI65913_LDOLN_VOLTAGE = 0x63, + TI65913_LDOUSB_CTRL = 0x64, + TI65913_LDOUSB_VOLTAGE = 0x65, + + TI65913_LDO_CTRL = 0x6A, + TI65913_LDO_PD_CTRL1 = 0x6B, + TI65913_LDO_PD_CTRL2 = 0x6C, + + TI65913_LDO_SHORT_STATUS1 = 0x6D, + TI65913_LDO_SHORT_STATUS2 = 0x6E, }; void pmic_init(unsigned bus); -#endif /* __MAINBOARD_GOOGLE_RUSH_PMIC_H__ */ +#endif /* __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__ */ |