diff options
| author | Furquan Shaikh <furquan@google.com> | 2014-11-10 23:22:01 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-10 12:00:37 +0200 |
| commit | ad73c4521b3512522d4b1728a5c280ae677f12f4 (patch) | |
| tree | 489e02f5768eb88ea4d4b9f373620a1c9148ed75 /src/mainboard/google/rush_ryu | |
| parent | a545778d133958712e0d7b317600bf066d688e22 (diff) | |
| download | coreboot-ad73c4521b3512522d4b1728a5c280ae677f12f4.tar.xz | |
ryu: Select pwr btn polarity based on board id
Proto 0,1,2 boards had pwr btn active high. Proto 3 onwards boards will have pwr
btn active low. Thus, select power btn polarity based on board id.
BUG=chrome-os-partner:33545
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt on ryu proto 1.
Change-Id: I9b06b10358b91d40cfdb418ef8cf4da1ae833121
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7100a42b53a09ed4cb298f88d6f804f46fecacb5
Original-Change-Id: Icdf51b9324385de00f5787e81018518c5397215f
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229011
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9418
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/rush_ryu')
| -rw-r--r-- | src/mainboard/google/rush_ryu/chromeos.c | 15 | ||||
| -rw-r--r-- | src/mainboard/google/rush_ryu/gpio.h | 6 | ||||
| -rw-r--r-- | src/mainboard/google/rush_ryu/romstage.c | 2 |
3 files changed, 16 insertions, 7 deletions
diff --git a/src/mainboard/google/rush_ryu/chromeos.c b/src/mainboard/google/rush_ryu/chromeos.c index f752aeee6c..2fd9bb1048 100644 --- a/src/mainboard/google/rush_ryu/chromeos.c +++ b/src/mainboard/google/rush_ryu/chromeos.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <boardid.h> #include <boot/coreboot_tables.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> @@ -26,6 +27,14 @@ #include "gpio.h" +static inline uint32_t get_pwr_btn_polarity(void) +{ + if (board_id() < BOARD_ID_PROTO_3) + return ACTIVE_HIGH; + + return ACTIVE_LOW; +} + void fill_lb_gpios(struct lb_gpios *gpios) { int count = 0; @@ -48,9 +57,9 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* TODO(adurbin): add lid switch */ - /* Power: active low */ - gpios->gpios[count].port = POWER_BUTTON_INDEX, - gpios->gpios[count].polarity = ACTIVE_HIGH; + /* Power: active low / high depending on board id */ + gpios->gpios[count].port = POWER_BUTTON_INDEX; + gpios->gpios[count].polarity = get_pwr_btn_polarity(); gpios->gpios[count].value = gpio_get(POWER_BUTTON); strncpy((char *)gpios->gpios[count].name, "power", GPIO_MAX_NAME_LENGTH); diff --git a/src/mainboard/google/rush_ryu/gpio.h b/src/mainboard/google/rush_ryu/gpio.h index 839edc04d0..89f32801f0 100644 --- a/src/mainboard/google/rush_ryu/gpio.h +++ b/src/mainboard/google/rush_ryu/gpio.h @@ -58,9 +58,9 @@ enum { SPI_1V8_WP_L = GPIO(R1), WRITE_PROTECT_L = SPI_1V8_WP_L, WRITE_PROTECT_L_INDEX = GPIO_R1_INDEX, - /* Power Button -- actually active high, but the net names are off. */ - BTN_AP_PWR_L = GPIO(Q0), - POWER_BUTTON = BTN_AP_PWR_L, + /* Power button - Depending on board id, maybe active high / low */ + BTN_AP_PWR = GPIO(Q0), + POWER_BUTTON = BTN_AP_PWR, POWER_BUTTON_INDEX = GPIO_Q0_INDEX, }; diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c index fc2379f9b3..4a13b898c4 100644 --- a/src/mainboard/google/rush_ryu/romstage.c +++ b/src/mainboard/google/rush_ryu/romstage.c @@ -39,7 +39,7 @@ static const struct pad_config padcfgs[] = { PAD_CFG_GPIO_OUT0(KB_ROW12, PINMUX_PULL_DOWN), /* MDM_DET - expected to be pulled down by LTE modem */ PAD_CFG_GPIO_INPUT(GPIO_PV1, PINMUX_PULL_UP), - /* Power Button - active high */ + /* Power Button - active high / low depending on board id */ PAD_CFG_GPIO_INPUT(KB_COL0, PINMUX_PULL_UP), /* BTN_AP_VOLD_L - active low */ PAD_CFG_GPIO_INPUT(KB_COL6, PINMUX_PULL_UP), |