samus: Combine mainboard patches to build soc/intel/broadwell

Combine four patches dependencies. These will not build
individually, so combine them for coreboot.org upstream.

samus: Move SPD handling to separate file

The code to find the SPD data for the mainboard based on GPIOs
is moved from romstage.c into spd.c.

It relies on the updated pei_data structure from broadwell instead
of the haswell interface.

BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751

Original-Change-Id: I5bd56f81884dae117b35a1ffa5fb6e804fd3cb9c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199920
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 0bd2de4ba5eb8ba5e9d43f8e82ce9ff7587eab62)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

samus: Move PEI data structure init to separate file

This needs to be executed in both romstage and ramstage
for the different PEI binary stages.

It uses the broadwell interface now instead of haswell.

BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751

Original-Change-Id: Ida05bd17b9e54f08ed0e2767361c9301a2e97709
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199921
(cherry picked from commit 89f98a27ea561ec63e716b1f6446d92822a6a5de)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

samus: Convert mainboard to use soc/intel/broadwell

Switch from the haswell cpu/northbridge/southbridge interface
to the soc/intel/broadwell interface.

- Use new headers where appropriate
- Remove code that is now done by the SOC generic code
- Update GPIO map to drop LP specific handling
- Update INT15 handlers, drop all but the boot display hook

BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751

Original-Change-Id: I56f3543612e89e2cdb4256b1bcd4279f5546b918
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199922

(cherry picked from commit 715dbb06e9f79d1ec3647330311c45aa29362375)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

samus: Add some code to print basic info from SPD

The handling of LPDDR is a bit messy in Intel platforms.  There
is no traditional SPD so instead one is created by hand from the
provided datasheets.

These have varying (and sometimes unexpected) geometry and it can
be important during bringup to know what configuration is being
passed to the memory training code.

This could in theory be put in a more generic location, but for now
this is the only board with LPDDR3 where I have found it valuable.

BUG=chrome-os-partner:28234
TEST=Build and boot on samus, look for SPD details on the console.
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751

Original-Change-Id: Ibce0187ceb77d37552ffa1b4a5935061d7019259
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199923
(cherry picked from commit 3f36348dd7abc67048407f181065f1a99b3d0dab)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I1d19dffbd0b2e838d1946670a0bee9f8e121869d
Reviewed-on: http://review.coreboot.org/7943
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

1 files changed, 69 insertions, 92 deletions

diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb
index 12a21ecdb0..3e87eca103 100644
--- a/src/mainboard/google/samus/devicetree.cb
+++ b/src/mainboard/google/samus/devicetree.cb
@@ -1,4 +1,4 @@
-chip northbridge/intel/haswell
+chip soc/intel/broadwell
 
 	# Enable eDP Hotplug with 6ms pulse
 	register "gpu_dp_d_hotplug" = "0x06"
@@ -21,104 +21,81 @@ chip northbridge/intel/haswell
 	register "gpu_panel_power_backlight_on_delay" = "2000"	# 200ms
 	register "gpu_panel_power_backlight_off_delay" = "2000"	# 200ms
 
-	device cpu_cluster 0 on
-		chip cpu/intel/socket_rPGA989
-			device lapic 0 on end
-		end
-		chip cpu/intel/haswell
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-
-			register "c1_battery" = "2"	# ACPI(C1) = MWAIT(C1E)
-			register "c2_battery" = "9"	# ACPI(C2) = MWAIT(C7S)
-			register "c3_battery" = "12"	# ACPI(C3) = MWAIT(C10)
-
-			register "c1_acpower" = "2"	# ACPI(C1) = MWAIT(C1E)
-			register "c2_acpower" = "9"	# ACPI(C2) = MWAIT(C7S)
-			register "c3_acpower" = "12"	# ACPI(C3) = MWAIT(C10)
-		end
-	end
-
-	device domain 0 on
-		device pci 00.0 on end # host bridge
-		device pci 02.0 on end # vga controller
-		device pci 03.0 on end # mini-hd audio
+	register "pirqa_routing" = "0x8b"
+	register "pirqb_routing" = "0x8a"
+	register "pirqc_routing" = "0x8b"
+	register "pirqd_routing" = "0x8b"
+	register "pirqe_routing" = "0x80"
+	register "pirqf_routing" = "0x80"
+	register "pirqg_routing" = "0x80"
+	register "pirqh_routing" = "0x80"
 
-		chip southbridge/intel/lynxpoint
-			register "pirqa_routing" = "0x8b"
-			register "pirqb_routing" = "0x8a"
-			register "pirqc_routing" = "0x8b"
-			register "pirqd_routing" = "0x8b"
-			register "pirqe_routing" = "0x80"
-			register "pirqf_routing" = "0x80"
-			register "pirqg_routing" = "0x80"
-			register "pirqh_routing" = "0x80"
+	# EC range is 0x800-0x9ff
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x00fc0901"
 
-			# EC range is 0x800-0x9ff
-			register "gen1_dec" = "0x00fc0801"
-			register "gen2_dec" = "0x00fc0901"
+	# EC_SMI is GPIO34
+	register "alt_gp_smi_en" = "0x0004"
+	register "gpe0_en_1" = "0x00000000"
+	# EC_SCI is GPIO36
+	register "gpe0_en_2" = "0x00000010"
+	register "gpe0_en_3" = "0x00000000"
+	register "gpe0_en_4" = "0x00000000"
 
-			# EC_SMI is GPIO34
-			register "alt_gp_smi_en" = "0x0004"
-			register "gpe0_en_1" = "0x00000000"
-			# EC_SCI is GPIO36
-			register "gpe0_en_2" = "0x00000010"
-			register "gpe0_en_3" = "0x00000000"
-			register "gpe0_en_4" = "0x00000000"
+	register "sata_port_map" = "0x1"
+	register "sio_acpi_mode" = "0"
 
-			register "ide_legacy_combined" = "0x0"
-			register "sata_ahci" = "0x1"
-			register "sata_port_map" = "0x1"
+	# Force enable ASPM for PCIe Port 1
+	register "pcie_port_force_aspm" = "0x01"
 
-			register "sio_acpi_mode" = "0"
-			register "sio_i2c0_voltage" = "0" # 3.3V
-			register "sio_i2c1_voltage" = "0" # 3.3V
+	# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
+	register "icc_clock_disable" = "0x013e0000"
 
-			# Force enable ASPM for PCIe Port 1
-			register "pcie_port_force_aspm" = "0x01"
+	# Enable S0ix
+	register "s0ix_enable" = "1"
 
-			# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
-			register "icc_clock_disable" = "0x013e0000"
-
-			# Route all USB ports to XHCI per default
-			register "xhci_default" = "1"
-
-			device pci 13.0 on end # Smart Sound Audio DSP
-			device pci 14.0 on end # USB3 XHCI
-			device pci 15.0 on end # Serial I/O DMA
-			device pci 15.1 on end # I2C0
-			device pci 15.2 on end # I2C1
-			device pci 15.3 off end # GSPI0
-			device pci 15.4 off end # GSPI1
-			device pci 15.5 off end # UART0
-			device pci 15.6 off end # UART1
-			device pci 16.0 on end # Management Engine Interface 1
-			device pci 16.1 off end # Management Engine Interface 2
-			device pci 16.2 off end # Management Engine IDE-R
-			device pci 16.3 off end # Management Engine KT
-			device pci 17.0 off end # SDIO
-			device pci 19.0 off end # GbE
-			device pci 1b.0 off end # High Definition Audio
-			device pci 1c.0 on end # PCIe Port #1
-			device pci 1c.1 off end # PCIe Port #2
-			device pci 1c.2 off end # PCIe Port #3
-			device pci 1c.3 off end # PCIe Port #4
-			device pci 1c.4 off end # PCIe Port #5
-			device pci 1c.5 off end # PCIe Port #6
-			device pci 1d.0 on end # USB2 EHCI
-			device pci 1e.0 off end # PCI bridge
-			device pci 1f.0 on
-				chip ec/google/chromeec
-					# We only have one init function that
-					# we need to call to initialize the
-					# keyboard part of the EC.
-					device pnp ff.1 on # dummy address
-					end
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # host bridge
+		device pci 02.0 on  end # vga controller
+		device pci 03.0 on  end # mini-hd audio
+		device pci 13.0 on  end # Smart Sound Audio DSP
+		device pci 14.0 on  end # USB3 XHCI
+		device pci 15.0 on  end # Serial I/O DMA
+		device pci 15.1 on  end # I2C0
+		device pci 15.2 on  end # I2C1
+		device pci 15.3 off end # GSPI0
+		device pci 15.4 off end # GSPI1
+		device pci 15.5 off end # UART0
+		device pci 15.6 off end # UART1
+		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT
+		device pci 17.0 off end # SDIO
+		device pci 19.0 off end # GbE
+		device pci 1b.0 off end # High Definition Audio
+		device pci 1c.0 on  end # PCIe Port #1
+		device pci 1c.1 off end # PCIe Port #2
+		device pci 1c.2 off end # PCIe Port #3
+		device pci 1c.3 off end # PCIe Port #4
+		device pci 1c.4 off end # PCIe Port #5
+		device pci 1c.5 off end # PCIe Port #6
+		device pci 1d.0 off end # USB2 EHCI
+		device pci 1e.0 off end # PCI bridge
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
 				end
-			end # LPC bridge
-			device pci 1f.2 on end # SATA Controller
-			device pci 1f.3 off end # SMBus
-			device pci 1f.6 on end # Thermal
-		end
+			end
+		end # LPC bridge
+		device pci 1f.2 on  end # SATA Controller
+		device pci 1f.3 off end # SMBus
+		device pci 1f.6 on  end # Thermal
 	end
 end