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authorDuncan Laurie <dlaurie@chromium.org>2014-07-15 13:41:18 -0700
committerMarc Jones <marc.jones@se-eng.com>2015-01-19 22:17:16 +0100
commit808a254c3f38e85d97758d8551bd423ab5e9ef05 (patch)
treef8268af02b6e5570a938468617a6fce79defb766 /src/mainboard/google/samus/gpio.h
parent6a342cb699d3573e366053076df5808c738de7e6 (diff)
downloadcoreboot-808a254c3f38e85d97758d8551bd423ab5e9ef05.tar.xz
samus: Delay bringing SSD out of reset
In order to ensure that we meet timing requirements for the SSD power sequencing delay bringing the SSD out of reset until after memory training. BUG=chrome-os-partner:29914 BRANCH=None TEST=build and boot on samus Original-Change-Id: I807e3d3698255287c3fe7219f44e8ec9a0985df1 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208155 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1cf557049c49e1ba11ade1eee7a45fc2b075ff3d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib39a14a03e04a167fab45b58b3bc840eb4bcf317 Reviewed-on: http://review.coreboot.org/8215 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google/samus/gpio.h')
-rw-r--r--src/mainboard/google/samus/gpio.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h
index c2f5fdea15..806804c719 100644
--- a/src/mainboard/google/samus/gpio.h
+++ b/src/mainboard/google/samus/gpio.h
@@ -23,6 +23,7 @@
#include <broadwell/gpio.h>
#define SAMUS_GPIO_PP3300_AUTOBAHN_EN 23
+#define SAMUS_GPIO_SSD_RESET_L 47
static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 0: UNUSED */
@@ -72,7 +73,7 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 44: UNUSED */
PCH_GPIO_PIRQ, /* 45: DSP_INT (PIRQN) */
PCH_GPIO_PIRQ, /* 46: HOTWORD_DET_L (PIRQO) */
- PCH_GPIO_OUT_HIGH, /* 47: SSD_RESET_L */
+ PCH_GPIO_OUT_LOW, /* 47: SSD_RESET_L */
PCH_GPIO_UNUSED, /* 48: UNUSED */
PCH_GPIO_UNUSED, /* 49: UNUSED */
PCH_GPIO_UNUSED, /* 50: UNUSED */