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authorDuncan Laurie <dlaurie@chromium.org>2015-09-04 10:15:42 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-09-09 20:23:20 +0000
commit779caddec3c621f8bea667877b14cdfd339945e0 (patch)
tree4fb7ad868a030616388a4c72edd3541b14d8902f /src/mainboard/google/samus
parentab40b9196977de2c37e37fc28e98bea4596460a7 (diff)
downloadcoreboot-779caddec3c621f8bea667877b14cdfd339945e0.tar.xz
samus: Use EC PD kconfig instead of manual PD reboot
Use the new kconfig entry to select the EC PD chip and have it be rebooted before the EC automatically insetad of being done manually by the board. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-samus coreboot Change-Id: I9e7baffec500a83af1fcf9b1e43d418489172918 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 53b086725d9d595e8eff7e1e35b9ba8db17ca199 Original-Change-Id: I9c9a7dd2ba2b78d681b448839f2c5d15ba9dfe60 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297748 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11572 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/samus')
-rw-r--r--src/mainboard/google/samus/Kconfig1
-rw-r--r--src/mainboard/google/samus/romstage.c1
2 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig
index 3059b4bcf1..d8509fbca8 100644
--- a/src/mainboard/google/samus/Kconfig
+++ b/src/mainboard/google/samus/Kconfig
@@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOC_INTEL_BROADWELL
select BOARD_ROMSIZE_KB_8192
select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_PD
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c
index 50e633bfd4..d9efdd471e 100644
--- a/src/mainboard/google/samus/romstage.c
+++ b/src/mainboard/google/samus/romstage.c
@@ -45,7 +45,6 @@ void mainboard_romstage_entry(struct romstage_params *rp)
printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version());
/* Ensure the EC and PD are in the right mode for recovery */
- google_chromeec_early_pd_init();
google_chromeec_early_init();
/* Initialize GPIOs */