diff options
author | Duncan Laurie <dlaurie@google.com> | 2019-06-13 10:46:54 -0700 |
---|---|---|
committer | Duncan Laurie <dlaurie@chromium.org> | 2019-06-13 21:13:58 +0000 |
commit | de666dc9b86452d5efbda70aa2364877d2fcd449 (patch) | |
tree | 2362885ae75cb63d83dfb2ad0880ad2bc2d3ad5c /src/mainboard/google/sarien/ramstage.c | |
parent | 7945f7541717f07c038a0fa4c38130bb1128e2d8 (diff) | |
download | coreboot-de666dc9b86452d5efbda70aa2364877d2fcd449.tar.xz |
mb/google/sarien: Disable unused GPIOs
These 4 GPIOs are being disconnected in the next board so use the
board ID to configure these pins as not connected to ensure
they do not cause leakage.
Also remove the ACPI _PTS S5 code that was configuring the GPIOs.
This does mean they will cause small leakage in S5 on existing boards,
but it will not affect the new boards.
BUG=b:132393441
TEST=boot on sarien with fake board ID and ensure that coreboot
configures these pads as expected.
Change-Id: I6ac04b9a635829811a09aeab7cba3bb58cfcff47
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Diffstat (limited to 'src/mainboard/google/sarien/ramstage.c')
-rw-r--r-- | src/mainboard/google/sarien/ramstage.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index 1d220461cf..811afa1b16 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -14,6 +14,7 @@ */ #include <arch/acpi.h> +#include <boardid.h> #include <drivers/vpd/vpd.h> #include <smbios.h> #include <soc/gpio.h> @@ -60,6 +61,13 @@ void smbios_fill_dimm_locator(const struct dimm_info *dimm, } #endif +static const struct pad_config gpio_unused[] = { +/* SUSWARN# */ PAD_NC(GPP_A13, NONE), +/* SUSACK# */ PAD_NC(GPP_A15, NONE), +/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), +/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), +}; + void mainboard_silicon_init_params(FSP_S_CONFIG *params) { const struct pad_config *gpio_table; @@ -67,6 +75,10 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) gpio_table = variant_gpio_table(&num_gpios); cnl_configure_pads(gpio_table, num_gpios); + + /* Disable unused pads for devices with board ID > 2 */ + if (board_id() > 2) + gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused)); } static void mainboard_enable(struct device *dev) |