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| author | Ivy Jian <ivy_jian@compal.corp-partner.google.com> | 2020-06-16 15:22:47 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-07-23 17:05:38 +0000 |
| commit | 311ddbd193dd0702b8f506ace32facf6402b6e8e (patch) | |
| tree | 737c181515da861e38fb56868169af1ccf2c5bd5 /src/mainboard/google/sarien/variants | |
| parent | d54c9b0fef7289c948070d98dc9aeae56072db68 (diff) | |
| download | coreboot-311ddbd193dd0702b8f506ace32facf6402b6e8e.tar.xz | |
mb/google/sarien: Enable bayhub 720 on Sarien
Add PCIe-eMMC bridge bayhub 720 on Sarien.
BUG=b:157971972
BRANCH=sarien
TEST=local build and boot from storage successfully
Change-Id: I28f40a420d51f476487655548f386cfbdc2e5329
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Diffstat (limited to 'src/mainboard/google/sarien/variants')
| -rw-r--r-- | src/mainboard/google/sarien/variants/sarien/devicetree.cb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 09b4240993..1a8e62454b 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -395,12 +395,20 @@ chip soc/intel/cannonlake device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on end # PCI Express Port 8 device pci 1d.0 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 |