summaryrefslogtreecommitdiff
path: root/src/mainboard/google/sarien
diff options
context:
space:
mode:
authorRoy Mingi Park <roy.mingi.park@intel.com>2019-04-13 15:16:50 -0700
committerDuncan Laurie <dlaurie@chromium.org>2019-04-22 18:00:13 +0000
commite3f5f2155a75687ab50d53c49977748f4cecdb2b (patch)
treefa5685287348d53950039350033a045c37ea7811 /src/mainboard/google/sarien
parentc94ba798d6f3aa3bf49f6d00d7bb18a4cc00268f (diff)
downloadcoreboot-e3f5f2155a75687ab50d53c49977748f4cecdb2b.tar.xz
mb/google/sarien: Configure both GPP_H12 and GPP_H13 for SSD on Arcada
Currently, Arcada only supports D3hot during S0iX and there is leakage power around 5~10mW depending on SSD vendors. To support D3cold for SSD during S0iX, one MOSFET will be added on DVT2 and two GPIOs are required to be configured. GPP_H13 is to control SSD_SCP_PWR_EN(power enable) and GPP_H12 is to control SSD reset. BUG=b:130741066 TEST=Measure SSD power during S0iX from Arcada(DVT2) Change-Id: I868590e9e85d5df07930a3681884e3fc3a5c4d50 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32361 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/sarien')
-rw-r--r--src/mainboard/google/sarien/variants/arcada/gpio.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c
index b66e1dda43..2a0ead82a9 100644
--- a/src/mainboard/google/sarien/variants/arcada/gpio.c
+++ b/src/mainboard/google/sarien/variants/arcada/gpio.c
@@ -211,8 +211,8 @@ static const struct pad_config gpio_table[] = {
/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */
/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */
-/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE),
-/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE),
+/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */
+/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */
/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),
/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */
/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE),