diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2019-01-25 15:22:24 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-02-20 23:44:37 +0000 |
| commit | 5620b105461cc18cf1439f02013153237f372b4b (patch) | |
| tree | d118584de4346898681a86ecf0a48ac9278f968d /src/mainboard/google/sarien | |
| parent | 31b4eb6c4a77053b1ce690a476a8565f25c7ebd2 (diff) | |
| download | coreboot-5620b105461cc18cf1439f02013153237f372b4b.tar.xz | |
src/soc/intel/cannonlake: Add _DSM methods for LPIT table
This patch adds the _DSM method 5 and 6 for entering and exiting S0ix.
The _DSM method gets injected into DSDT table and called from kernel.
LPIT table is hardcoded in this patch but the proper way to implement
is to use inject_dsdt to make the _DSM methods available for soc's to
implement.
Calling the LPIT table from mainboard here so that with the current
implementation the platforms which do not have lpit support throw
compilation error.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db
Reviewed-on: https://review.coreboot.org/c/31101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google/sarien')
| -rw-r--r-- | src/mainboard/google/sarien/dsdt.asl | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index e5e48bb3a7..547253fef0 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -50,6 +50,9 @@ DefinitionBlock( /* Chipset specific sleep states */ #include <soc/intel/cannonlake/acpi/sleepstates.asl> + /* Low power idle table */ + #include <soc/intel/cannonlake/acpi/lpit.asl> + #if IS_ENABLED(CONFIG_EC_GOOGLE_WILCO) /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) |